Fremont, CA, United States
Fremont, CA, United States

STATS ChipPAC STATS ChipPAC Ltd. is a service provider of full turnkey semiconductor packaging design, bump, probe, assembly, test and distribution solutions. STATS ChipPAC provides semiconductor packaging and test services to a diversified global customer base servicing the computing, communications and consumer markets. STATS ChipPAC’s customers include some of the largest semiconductor companies in the world.Headquartered in Singapore, STATS ChipPAC has manufacturing facilities in South Korea, Singapore, China, Malaysia and Taiwan .STATS ChipPAC customer support offices are located in the United States . Offices outside the United States are located in Singapore, South Korea, China, Malaysia, Taiwan, Japan, Switzerland, the United Kingdom and the Netherlands. In addition, STATS ChipPAC has research and development centers in South Korea, Singapore, Malaysia, China, Taiwan and the United States.STATS ChipPAC is listed on the Singapore Exchange Securities Trading Limited . Wikipedia.


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A semiconductor device comprises a semiconductor die including a conductive layer. A first insulating layer is formed over the semiconductor die and conductive layer. An encapsulant is disposed over the semiconductor die. A compliant island is formed over the first insulating layer. An interconnect structure is formed over the compliant island. An under bump metallization (UBM) is formed over the compliant island. The compliant island includes a diameter greater than 5 m larger than a diameter of the UBM. An opening is formed in the compliant island over the conductive layer. A second insulating layer is formed over the first insulating layer and compliant island. A third insulating layer is formed over an interface between the semiconductor die and the encapsulant. An opening is formed in the third insulating layer over the encapsulant for stress relief.


Approaches, techniques, and mechanisms are disclosed for a method of manufacturing an integrated circuit package with a single-layer substrate. In an embodiment, the inventive integrated circuit package not only reduces manufacture cost but also improves reliability and miniaturization. According to an embodiment, a single-layer substrate is manufactured using non-photoimageable dielectric (NPID) material that is different from other dielectric materials, such as PrePreg (PPG) materials, copper clad laminates (CCL), solder resists (SR), and so forth, that are used in conventional substrates. A single-layer substrate manufactured using the NPID material provides a low cost solution by, among other aspects, eliminating certain process steps, such as a laser drill process, that are often used to manufacture the other substrates. According to an embodiment, the NPID material utilized for the described techniques and systems may feature a low coefficient of thermal expansion (CTE), a high glass transition temperature (Tg), and/or a high modulus compared to the other dielectric materials. Such features improve reliability because of, among other aspects, improved trace protection and peel strength, thereby enhancing adhesion between traces (e.g., of copper (Cu), etc.) and dielectric materials. In an embodiment, such features also improve miniaturization because, for example, the NPID material may allow formation of traces with reduced geometry.


A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.


A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.


A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.


A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. The substrate can be a wafer-shape, panel, or singulated form. The conductive posts can have a circular, rectangular, tapered, or narrowing intermediate shape. A semiconductor die is disposed through an opening in the base between the conductive posts. The semiconductor die extends above the conductive posts or is disposed below the conductive posts. An encapsulant is deposited over the semiconductor die and around the conductive posts. The base and a portion of the encapsulant is removed to electrically isolate the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts. An insulating layer is formed over the semiconductor die, encapsulant, and conductive posts. A semiconductor package is disposed over the semiconductor die and electrically connected to the conductive posts.


A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant.


A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.


A system is described for interactively analyzing plays of a sporting event based on real-world positional tracking data. Using positional information regarding the players and/or ball and/or other objects obtained from a tracking system, along with identified event data and contextual information, the system processes a library of plays (e.g., one or more seasons worth of a leagues contests) into a searchable database of plays using multiple alignment templates and discriminative clustering techniques. A user interface is described for interacting with the database in a graphical manner, whereby users can query a graphical depiction of a play and receive the most similar plays from the library, along with statistical information relating to the plays. The user interface further permits the user to modify the query graphically (e.g., moving or exchanging players, ball trajectories, etc.) and obtain updated statistical information for comparison.


An integrated circuit packaging system and method of manufacture thereof includes: a dielectric core having an embedded pad; a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist layer; a device interconnect attached to the embedded pad; and an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect for mounting the integrated circuit device to the dielectric core.

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