Yu Z.,State Key Laboratory of ASIC and Systems |
Su J.,State Key Laboratory of ASIC and Systems |
Yang F.,State Key Laboratory of ASIC and Systems |
Su Y.,Fudan University |
And 5 more authors.
Proceedings - IEEE International Symposium on Circuits and Systems | Year: 2016
This paper presents a fast compressive sensing reconstruction algorithm implemented on FPGA using Orthogonal Matching Pursuit (OMP). The algorithm is optimized with QR decomposition to solve the least square problem and avoids the square root operations to facilitate the hardware implementation. The implementation results show that this design can run at a frequency of 100MHz and the proposed algorithm achieves 50% lower complexity than the other existed algorithms. © 2016 IEEE.
Shu G.,State Key Laboratory of ASIC and Systems |
Guo Y.,State Key Laboratory of ASIC and Systems |
Ren J.,State Key Laboratory of ASIC and Systems |
Ren J.,Fudan University |
And 2 more authors.
Analog Integrated Circuits and Signal Processing | Year: 2011
This paper presents a 10-bit 40-MS/s pipelined analog-to-digital converter (ADC) in a 0.13-μm CMOS process for subsampling applications. A simplified opamp-sharing scheme between two successive pipelined stages is proposed to reduce the power consumption. For subsampling, a cost-effective fast input-tracking switch with high linearity is introduced to sample the input signal up to 75 MHz. A two-stage amplifier with hybrid frequency compensation is developed to achieve both high bandwidth and large swing with low power dissipation. The measured result shows that the ADC achieves over 77 dB spurious free dynamic range (SFDR) and 57.3 dB signal-to-noise-plus-distortion ratio (SNDR) within the first Nyquist zone and maintains over 70 dB SFDR and 55.3 dB SNDR for input signal up to 75 MHz. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are ±0.2 LSB and ±0.3 LSB, respectively. The ADC consumes 15.6 mW at the sampling rate of 40 MHz from a 1.2-V supply voltage, and achieves a figure-of-merit (FOM) value of 0.22 pJ per conversion step. © 2011 Springer Science+Business Media, LLC.