State Key Laboratory of ASIC and System

Shanghai, China

State Key Laboratory of ASIC and System

Shanghai, China
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Gu W.,State Key Laboratory of ASIC and System | Wu Y.,State Key Laboratory of ASIC and System | Ye F.,State Key Laboratory of ASIC and System | Ren J.,State Key Laboratory of ASIC and System | Ren J.,Fudan University
Journal of Semiconductors | Year: 2015

This paper presents a single-ended 8-channel 10-bit 200 kS/s 607 μW synchronous successive approximation register (SAR) analog-to-digital converter (ADC) using HLMC 55 nm low leakage (LL) CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows exponentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607 μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and-distortion ratio (SNDR) is 60.1 dB and the spurious-free dynamic range (SFDR) is 68.1 dB. The measured DNL is +0.37/-0.06 LSB and INL is +0.58/-0.22 LSB. © 2015 Chinese Institute of Electronics.


Gu W.,State Key Laboratory of ASIC and System | Ye F.,State Key Laboratory of ASIC and System | Ren J.,State Key Laboratory of ASIC and System | Ren J.,Fudan University
Journal of Semiconductors | Year: 2014

This paper presents an 11-bit 22-MS/s 0.6-mW successive approximation register (SAR) analog-to-digital converter (ADC) using SMIC 65-nm low leakage (LL) CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio (SNDR) is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step. © 2014 Chinese Institute of Electronics.


Lin J.,State Key Laboratory of ASIC and System | Lin J.,Fudan University | Ye F.,State Key Laboratory of ASIC and System | Ye F.,Fudan University | And 2 more authors.
Proceedings - 2014 IEEE 12th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2014 | Year: 2014

For solving the problem of non-ideal factors introduced from the analog front-end in Orthogonal Frequency Division Multiplexing (OFDM) systems, a joint estimation method of Carrier Frequency Offset (CFO) and Sampling Frequency Offset (SFO) is proposed. This algorithm uses three consecutive preamble symbols to estimate and is robust to large I/Q imbalance. It can reduce interference of Gaussian noise by considering all the samples and taking the advantage of them. Compared to the previous methods, the simulation results show that the proposed method can provide high precision in CFO and SFO estimation, which is robust to large-scale SNR and I/Q imbalance. © 2014 IEEE.


Su Y.,State Key Laboratory of ASIC and System | Xiang J.,State Key Laboratory of ASIC and System | Shen X.,State Key Laboratory of ASIC and System | Ye F.,State Key Laboratory of ASIC and System | And 2 more authors.
Journal of Semiconductors | Year: 2015

This paper presents a 1.12 Gb/s 11.3 mW transmitter using 0.18 μm mixed signal complementary metal-oxide semiconductor technology with a 1.8 V supply voltage. This transmitter implements a high-speed transmission with 1.2 V common-mode output voltage, adopting a low-voltage differential signaling (LVDS) technique. A multiplexer (MUX) and an LVDS driver are critical for a transmitter to complete a high-speed data transmission. This paper proposes a high power-efficiency single-stage 14 : 1 MUX and an adjustable LVDS driver circuit, capable of driving different loads with a slight increase in power consumption. The prototype chip implements a transmitter with a core area of 970 × 560 μm2, demonstrating low power consumption and adjustable driving capability. © 2015 Chinese Institute of Electronics.


Zhang Y.,State Key Laboratory of ASIC and System | Chen C.,State Key Laboratory of ASIC and System | Yu B.,State Key Laboratory of ASIC and System | Ye F.,State Key Laboratory of ASIC and System | And 2 more authors.
Journal of Semiconductors | Year: 2012

Sample-time error between channels degrades the resolution of time-interleaved analog-to-digital converters (TIADCs). A calibration method implemented in mixed circuits with low complexity and fast convergence is proposed in this paper. The algorithm for detecting sample-time error is based on correlation and widely applied to wide-sense stationary input signals. The detected sample-time error is corrected by a voltage-controlled sampling switch. The experimental result of a 2-channel 200-MS/s 14-bit TIADC shows that the signal-to-noise and distortion ratio improves by 19.1 dB, and the spurious-free dynamic range improves by 34.6 dB for a 70.12-MHz input after calibration. The calibration convergence time is about 20000 sampling intervals. © 2012 Chinese Institute of Electronics.


Wang X.-B.,Hebei University of Technology | Wang X.-B.,State Key Laboratory of ASIC and System | Zhao Z.-P.,Hebei University of Technology | Zhao Z.-P.,State Key Laboratory of ASIC and System | Feng Z.-H.,State Key Laboratory of ASIC and System
Wuli Xuebao/Acta Physica Sinica | Year: 2014

By the self-consistent solution of the Schrödinger and poisson equations, the effects of GaN channel layer, AlGaN back barrier layer with and without Si doping and AlN interlayer on two-dimensional electron gas in N-polar GaN/AlGaN heterostructure are systematically studied. The results indicate that the increases of the thickness values of GaN channel layer and AlGaN back barrier layer and Al content value can improve the density of 2DEG to a certain degree, and the influences of different Si doping forms on 2DEG sheet density are not the same, also the confinement of 2DEG could be strengthened by increasing Al content value and thickness value of the AlGaN barrier layer. The AlN interlayer is a comparatively outstanding one in improving the performance of the 2DEG such as the 2DEG sheet density and confinement. When GaN channel layer thickness is less than 5 nm, there is no 2DEG in the simulation, when it exceeds 20 nm the 2DEG sheet density tends to be saturated. 2DEG has a tendency to be saturated when the thickness value of AlGaN back barrier is more than 40 nm. 2DEG sheet densities with uniform doping and delta doping in AlGaN back barrier are saturated when the doping concentration is more than 5×1019 cm-3. The 2DEG sheet density could be increased from 0.93×1013 cm-2 without AlN interlayer to 1.17×1013 cm-2 with 2 nm AlN interlayer. © 2014 Chinese Physical Society.


Wang M.,State Key Laboratory of ASIC and System | Lin L.,Analog Devices Inc. | Ye F.,State Key Laboratory of ASIC and System | Ren J.,State Key Laboratory of ASIC and System
IEICE Electronics Express | Year: 2014

This paper presents a single-channel 1.0-GS/s 7-bit pipelined folding and interpolating analog-to-digital converter (PL-FAIADC) used in ultra wide band (UWB) system. An improved joint encoding method is proposed to eliminate the coarse sub-ADC and reduce the power consumption. Double-diode bootstrapped inter-stage switch is adopted to reach the pipelined working and improve the overall efficiency of speed. The ADC implemented in 0.13-μm CMOS technology achieves the signal-to-noise-and-distortion ratio (SNDR) of 37.89 dB and the spurious-free dynamic range (SFDR) of 45.89 dB for 498MHz input frequency at the rate of 1.0GS/s. The power consumption is 98mW with sampling rate of 1.0GS/s and supply voltage of 1.2/ 2.5 V. The peak figure-of-merit (FoM) is 1.54 pJ/conversion-step. © IEICE 2014.


Yan L.,State Key Laboratory of ASIC and System | Li L.,State Key Laboratory of ASIC and System | Jiefeng X.,State Key Laboratory of ASIC and System | Fan Y.,State Key Laboratory of ASIC and System | Junyan R.,State Key Laboratory of ASIC and System
Journal of Semiconductors | Year: 2010

A 1.4-V 8-bit 300-MS/s folding and interpolating analog-to-digital converter (ADC) is proposed. Fabricated in the 0.13-μm CMOS process and occupying only 0.6-mm 2 active area, the ADC is especially suitable for embedded applications. The system is optimized for a low-power purpose. Pipelining sampling switches help to cut down the extra power needed for complete settling. An averaging resistor array is placed between two folding stages for power-saving considerations. The converter achieves 43.4-dB signal-to-noise and distortion ratio and 53.3-dB spurious-free dynamic range at 1-MHz input and 42.1-dB and 49.5-dB for Nyquist input. Measured results show a power dissipation of 34 mW and a figure of merit of 1.14 pJ/convstep at 250-MHz sampling rate at 1.4-V supply. © 2010 Chinese Institute of Electronics.

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