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Mathivanan V.,St. Joseph University in Tanzania | Haris M.,Karunya University
Optik | Year: 2016

Crystals of pure and Cu(NO3)2·3H2O doped Rochelle salt (sodium potassium tartrate) crystals are grown from solution at room temperature. The thermal studies such as TGA (thermo gravimetric analysis) shows that there are four stages of decomposition which is confirmed through the four endothermic peaks found in the DSC (differential scanning calorimetry) curve for both pure and Cu(NO3)2·3H2O doped Rochelle salt crystals. The magnetic susceptibility of the pure and doped crystals were found out to be 42.483 × 10-6 and 40.29 × 10-6 emu, respectively. Similarly, the magnetic moment of pure and doped crystals have been found out to be 3.19 BM and 3.10 BM, respectively. The antimicrobial activity of Pure and Cu(NO3)2·3H2O doped Rochelle salt crystals for various concentrations are explained in detail. The dielectric constant of pure and doped crystal decreases as the frequency of applied field increases at the end it gives diminishing value of dielectric constant. The dielectric nature of pure and doped crystals have been compared. The antimicrobial activity of pure and doped crystals shows the inhibition zone diameter for various concentrations with respect to E. coli and Staphylococcus aureus. © 2015 Elsevier GmbH.


Paulthurai A.,St. Joseph University in Tanzania | Dharmaraj B.,St. Joseph University in Tanzania
International Journal of Nanoelectronics and Materials | Year: 2014

Single Electron Tunneling (SET) technology introduces more potential for feature size decrease compared to well-established silicon-based CMOS technology. The SET technology offers the ability to control the motion of individual electrons in the designed circuits. In this paper, we present a single-electron 8-3 encoder built using single-electron devices. The circuit is designed using a proper tool based on a Monte Carlo technique. The complete schematic diagrams of these basic SEC along with the corresponding simulation results (using SIMON 2.0) of these SEC are included. First a single-electron OR gate is studied and then a Novel 8-3 Encoder SET, with detailed schematic and simulation results, is presented. The results proved that the circuit was an 8-3 encoder, while the behavior of the free energy of the system (which was calculated to be 4.90x10-1 eV) and the stability diagram verified the correct functioning of the circuit. © 2014, Universiti Malaysia Perlis. All rights reserved.


Arockia Linson A.,St. Joseph University in Tanzania | Paulthurai A.,St. Joseph University in Tanzania | Darmaraj B.,St. Joseph University in Tanzania
International Journal of Nanoelectronics and Materials | Year: 2014

The paper focused on the study to improve the mechanical and thermal stability of the composite material by adding fibre reinforced plastic and iron oxide nano fillers. The paper also on study of Nanocomposite material microstructures to find the effective characterization on oxide Nano fillers with epoxy resin and fibre reinforced plastic. Iron oxide nano particles were added in order to increase the strength without affecting the weight of the composite material which has been manufactured with epoxy resin and glass fibre. Varying the percentage of nano filler with epoxy resin we can modify the tensile strength and thermal stability of the composite body for our desire. Composite fabrication deals with two categories in making comparison process. The ordinary resin coated fibre reinforced plastic composite are compared with Nano added resin coated fibre reinforced plastic composite. The significant effect of iron oxide variation will be shown by the tensile and thermal stability test. © 2014, Universiti Malaysia Perlis. All rights reserved.


Senthil S.M.,St. Joseph University in Tanzania | Arockia J.S.,St. Joseph University in Tanzania | Arputharaj T.,St. Joseph University in Tanzania | Banupriya M.,St. Joseph University in Tanzania
2013 Pan African International Conference on Information Science, Computing and Telecommunications, PACT 2013 | Year: 2013

In this paper, a design of high performance and low power 4-bit Manchester carry look-ahead adder is presented with the help of modified multi-threshold domino logic technique. The introduced MT-MOS transistors decrease the power dissipation of adder circuit by reducing sub threshold leakage current. The FTL dynamic logic is another technique used to increase operating speed of logic circuit, which evaluates the computational blocks partially before the input signals are formalized and then the final evaluation is performed as soon as the input signals arrive. The pre-evaluation logic reduces propagation delay into half. The combination of FTL dynamic logic and MT-CMOS domino logic techniques are yields high fan-out, high switching frequencies since both lower delay and dynamic low power consumption in the arithmetic circuits. A Manchester structure of carry generation employed in carry look-ahead adder minimizes the area of arithmetic circuit by decreasing number of transistors. The simulation results have verified that the proposed techniques are reduced the total power dissipation up to 40%, 55% of propagation delay than the standard dynamic domino CMOS technology. © 2013 IEEE.


Sivakumar M.S.,St. Joseph University in Tanzania | Murji J.,St. Joseph University in Tanzania | Jacob L.D.,St. Joseph University in Tanzania | Nyange F.,St. Joseph University in Tanzania | Banupriya M.,St. Joseph University in Tanzania
2013 Pan African International Conference on Information Science, Computing and Telecommunications, PACT 2013 | Year: 2013

In this paper, we propose an Intelligent Home Navigation System (IHNS) which comprises of a wheelchair, voice module and navigation module. This system can be used by an elderly or physically challenged person to move inside the home without any difficulty. In general, the elders may forget the way to the different rooms in house and the physically challenged people find hard to move the wheel chair without external aid. In the proposed system the wheelchair is operated automatically or manually by turning the wheels using hands or external aids. The proposed system is a voice controlled wheelchair robot. The voice of the person is detected by voice capture module and that compared with predefined voices loaded in the system by voice recognition module. According to the received voice, the destination is automatically understood and the wheelchair moves according to the route which is predefined. The system is also equipped with obstacle avoidance technique, where the person may not be able to provide proper voices at right time. The wheelchair can automatically navigate from one point to other in the home as per command from the voice module. © 2013 IEEE.


Arputharaj T.,St. Joseph University in Tanzania | Senthil S.M.,St. Joseph University in Tanzania | Arockia J.S.,St. Joseph University in Tanzania | Banupriya M.,St. Joseph University in Tanzania
2013 Pan African International Conference on Information Science, Computing and Telecommunications, PACT 2013 | Year: 2013

Active integrated antenna (AIA) is a new technology that integrates microstrip antennas with active solid state devices so that a number of interesting functions can be realized at low cost, simplicity of design and small size. In this paper, we are presenting a low noise active integrated antenna (LNAIA) that integrates active integrated antenna with low noise amplifier. This paper is designed to investigate the characteristics of patch antenna with direct integration of low noise amplifier at the design frequency of 2.5GHz. Design is analyzed with WIMAX standard and that ensured a capability of broad bandwidth and fast internet access. The LNA has the gain of 12dB and low noise figure of 2.4dB against the WIMAX design goal of > 10dB gain and > 7dB noise figure. The Antenna is designed and it has 44dB return loss and 6.3dB gain at 2.5GHz. While the LNAIA shows a better return loss of 49.66dB is 2.5GHz. This LNAIA has been designed and simulated by using CAD tool-Agilent ADS2002C-EM simulation software. © 2013 IEEE.


Senthil S.M.,St. Joseph University in Tanzania | Arockia J.S.,St. Joseph University in Tanzania | Arputharaj T.,St. Joseph University in Tanzania | Banupriya M.,St. Joseph University in Tanzania
2013 Pan African International Conference on Information Science, Computing and Telecommunications, PACT 2013 | Year: 2013

A design of multicarrier code division multiple access (MC-CDMA) receiver is proposed in this paper with novel low power parallel-pipelined FFT. The receiver is constructed based on number of sub-carrier systems which include two FFT blocks for demodulation, combiners for dispreading and equalizing the FFT outputs to recover the transmitted signals, and Viterbi decoder. The FFT architecture is constructed based on parallel-pipelined technique which includes different combination of hybrid low power techniques such as parallel-pipelined architectures, multiplier-less units which replace the complex multipliers in FFTs, low-power commutators based on an advanced interconnection, and low power butterfly architecture. Clock gating is extensively used in combiner to reduce power consumption by disabling the clock for the inactive circuits in FFT architecture. Viterbi decoder is implemented using trace back technique. It reduces the total power consumption to a considerable amount. By utilizing all the above techniques the design of proposed MC-CDMA receiver is implemented with Verilog HDL and synthesized in Cadence design tool using TSMC 0.18μm technology file. The result shows the overall power reduction about 48%, area reduction 23%. © 2013 IEEE.


Paulthurai A.,St. Joseph University in Tanzania | Dharmaraj B.,St. Joseph University in Tanzania
International Journal of Nanoelectronics and Materials | Year: 2013

An adder is an important element of all the arithmetic and logic units. The recent trend in Nanotechnology is moving towards the need of the devices, which consume low power. The Single Electron Transistor (SET), distinguished by a very small device size low power dissipation, high speed and high performance, is one of the most promising nano electronics devices to replace conventional CMOS. The SET technology offers the ability to control the motion of individual electrons in the designed circuits. In this Full Adder Circuit we were used 24 SET and 14 resistors. The circuit is functioning as required for all the combination of input voltage. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in SET process technology. Also shown is the considerable impact of the supply-voltage scaling on reducing the power expended by leakage and short-circuit. The Low-Power and High-Performance 1-Bit Set Full-Adder digital circuits have been simulated by PSPICE 9.1.


PubMed | St. Joseph University in Tanzania
Type: | Journal: SpringerPlus | Year: 2016

In this study the adsorption of Basic Violet, 14 from aqueous solution onto sulphuric acid activated materials prepared from Calophyllum inophyllum (CS) and Theobroma cacao (TS) shells were investigated. The experimental data were analysed by Langmuir, Freundlich and Temkin isotherm models. The results showed that CS has a superior adsorption capacity compared to the TS. The adsorption capacity was found to be 1416.43mg/g for CS and 980.39mg/g for TS. The kinetic data results at different concentrations were analysed using pseudo first-order and pseudo-second order model. Boyd plot indicates that the dye adsorption onto CS and TS is controlled by film diffusion. The adsorbents were characterised by scanning electron microscopy. The materials used in this study were economical waste products and hence can be an attractive alternative to costlier adsorbents for dye removal in industrial wastewater treatment processes.


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