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Newport, United Kingdom

Patent
SPTS Technologies | Date: 2014-11-04

According to the invention there is a method of depositing SiO


Patent
SPTS Technologies | Date: 2015-02-06

A method is for processing a substrate by physical vapour deposition (PVD). In the method, the substrate is supplied with a cooling gas so that during the PVD process, the substrate is lifted from a substrate support.


Patent
SPTS Technologies | Date: 2015-06-08

A substrate having a dielectric film thereon, in which: the dielectric film comprises at least four stacked layers of a dielectric material; the stacked layers comprise compressive layers which are subject to a compressive stress, and tensile layers which are subject to a tensile stress; and there are at least two spaced apart tensile layers which are each adjacent to one or more compressive layers.


Patent
SPTS Technologies | Date: 2015-04-03

A method is for etching a semiconductor substrate to reveal one or more features buried in the substrate. The method includes performing a first etch step using a plasma in which a bias power is applied to the substrate to produce an electrical bias, performing a second etch step without a bias power or with a bias power which is lower than the bias power applied during the first etch step, and alternately repeating the first and second etch steps.


Patent
SPTS Technologies | Date: 2014-05-23

An apparatus for processing a semiconductor workpiece includes a first chamber having a first plasma production source and a first gas supply for introducing a supply of gas into the first chamber, a second chamber having a second plasma production source and a second gas supply for introducing a supply of gas into the second chamber, a workpiece support positioned in the second chamber, and a plurality of gas flow pathway defining elements for defining a gas flow pathway in the vicinity of the workpiece when positioned on the workpiece support. The gas flow path defining elements include at least one wafer edge region protection element for protecting the edge of the wafer and/or a region outwardly circumjacent to the edge of the wafer, and at least one auxiliary element spaced apart from the wafer edge region protection element to define the gas flow pathway.

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