Spansion Inc. is an American-based company that designs, develops and manufactures flash memory microcontrollers, mixed-signal and analog products, as well as system-on-chip solutions. The company had more than 3,700 employees in 2014 and is headquartered in Sunnyvale, California. Spansion is a former joint-venture between AMD and Fujitsu. In August 2013, Spansion closed the acquisition of the Microcontroller and Analog Business of Fujitsu Semiconductor Limited.Spansion has more than 10,000 customers worldwide. Its products are used in the following markets: automotive electronics, home appliance, peripheral computing equipment, consumer equipment, industrial and networking. Wikipedia.
Spansion | Date: 2013-12-18
Various embodiments provide for topography aware optical proximity correction that can improve depth of focus during wafer lithography. The system can determine the topography of the wafer using real process information. The topographical variations can be based on random defects or structural details. The system can divide the wafer into regions based on the topography of the regions and determine depth of focus values for each of the regions. Optical proximity correction can then be performed on each region separately, using the separate defocus values to yield an accurate, topographically aware optical proximity correction model for the wafer. For regions with varying topography, optical proximity correction can be performed for two defocus values corresponding to the high and low extremes, such that the resulting simulated contour is satisfies a predetermined criterion associated with accuracy.
Spansion | Date: 2012-07-31
Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a source bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.
Spansion | Date: 2012-12-28
A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses.
Spansion and AMD Inc | Date: 2013-11-11
A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.
Spansion | Date: 2012-03-18
A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip.
Spansion | Date: 2011-03-23
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.
Spansion | Date: 2013-12-09
A computer-implemented method is disclosed for optimizing one or more sub-resolution assist features for use in a photolithographic process. The method may include incorporating a sub-resolution assist feature within a virtual photomask. The virtual photomask may then be modeled to produce a virtual print. One or more intensity values corresponding to the sub-resolution assist feature may be collected from the virtual print. Based on the one or more intensity values, a probability of having been printed may by assigned to the sub-resolution assist feature. In an iterative process, the probability may be used to optimize at least one of a location and size of the sub-resolution assist feature.
Spansion | Date: 2012-02-02
Retention of charges in a nonvolatile memory (NVM) cell having a nitride-based injector (such as SiN, SIRN, SiON) for facilitating injection of holes into a charge-storage layer (for NROM, nitride) of a charge-storage stack (for NROM, ONO) may be improved by providing an insulating layer (for NROM, oxide) between the charge-storage layer and the injector has a thickness of at least 3 nm. Top and bottom injectors are disclosed. Methods of operating NVM cells are disclosed. The NVM cell may be NROM, SONOS, or other oxide-nitride technology NVM cells such as SANOS, MANOS, TANOS.
Spansion | Date: 2013-03-18
A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.
News Article | February 21, 2017
MILPITAS, California, Feb. 21, 2017 /PRNewswire/ -- SEMI, the global association connecting and representing the worldwide electronics manufacturing supply chain, today announced the appointment of Ajit Manocha as its president and CEO. He will succeed Denny McGuirk, who announced his intention to retire last October. The SEMI International Board of Directors conducted a comprehensive search process, selecting Manocha, an industry leader with over 35 years of global experience in the semiconductor industry. Manocha will begin his new role on March 1 at SEMI's new Milpitas headquarter offices. "Ajit has a deep understanding of our industry's dynamics and the interdependence of the electronics manufacturing supply chain," said Y.H. Lee, chairman of SEMI's board of directors. "From his early days developing dry etch processes at AT&T Bell Labs, to running global manufacturing for Philips/NXP, Spansion, and, as CEO of GLOBALFOUNDRIES, Ajit has been formative to our industry's growth. Ajit is the ideal choice to drive our SEMI 2020 plan and beyond, ensuring that SEMI provides industry stewardship and engages its members to advance the interests of the global electronics manufacturing supply chain." "Beyond his experience leading some of our industry's top fabs, Ajit has long been active at SEMI and has served on boards of several global associations and consortia," said Denny McGuirk, retiring president and CEO of SEMI. "Ajit's experience in technology, manufacturing, and industry stewardship is a powerful combination. I'm very excited to be passing the baton to Ajit as he will continue to advance the growth and prosperity of SEMI's members." "I have tremendous respect for the work SEMI does on behalf of the industry," said Ajit Manocha, incoming president and CEO of SEMI. "I am excited to be joining SEMI at a time when our ecosystem is rapidly expanding due to extensive innovation on several fronts. From applications based on the Internet and the growth of mobile devices to artificial intelligence/machine learning, autonomous vehicles, and the Internet of Things, there is a much broader scope for SEMI to foster heterogeneous collaboration and fuel growth today than ever before. I am looking forward to leading the global SEMI organization as we strive to maximize value for our members across this extended global ecosystem." Manocha was formerly CEO at GLOBALFOUNDRIES, during which he also served as vice chairman and chairman of the Semiconductor Industry Association (SIA). Earlier, Manocha served as EVP of worldwide operations at Spansion. Prior to Spansion, Manocha was EVP and chief manufacturing officer at Philips/NXP Semiconductors. Manocha also held senior management positions within AT&T Microelectronics. He began his career at AT&T Bell Laboratories as a research scientist where he was granted several patents related to microelectronics manufacturing. Manocha holds a bachelor's degree from the University of Delhi and a master's degree in physical chemistry from Kansas State University. About SEMI SEMI® connects nearly 2,000 member companies and 250,000 professionals worldwide annually to advance the technology and business of electronics manufacturing. SEMI members are responsible for the innovations in materials, design, equipment, software, and services that enable smarter, faster, more powerful, and more affordable electronic products. Since 1970, SEMI has built connections that have helped its members grow, create new markets, and address common industry challenges together. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Seoul, Shanghai, Silicon Valley (Milpitas, Calif.), Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org and follow SEMI on LinkedIn and Twitter.