Entity

Time filter

Source Type

Sunnyvale, CA, United States

Spansion Inc. is an American-based company that designs, develops and manufactures flash memory microcontrollers, mixed-signal and analog products, as well as system-on-chip solutions. The company had more than 3,700 employees in 2014 and is headquartered in Sunnyvale, California. Spansion is a former joint-venture between AMD and Fujitsu. In August 2013, Spansion closed the acquisition of the Microcontroller and Analog Business of Fujitsu Semiconductor Limited.Spansion has more than 10,000 customers worldwide. Its products are used in the following markets: automotive electronics, home appliance, peripheral computing equipment, consumer equipment, industrial and networking. Wikipedia.


Patent
Spansion | Date: 2013-12-09

A computer-implemented method is disclosed for optimizing one or more sub-resolution assist features for use in a photolithographic process. The method may include incorporating a sub-resolution assist feature within a virtual photomask. The virtual photomask may then be modeled to produce a virtual print. One or more intensity values corresponding to the sub-resolution assist feature may be collected from the virtual print. Based on the one or more intensity values, a probability of having been printed may by assigned to the sub-resolution assist feature. In an iterative process, the probability may be used to optimize at least one of a location and size of the sub-resolution assist feature.


Patent
Spansion and AMD Inc | Date: 2013-11-11

A memory cell system is provided forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming an intermediate layer over the charge trap layer, and forming a second insulator layer with the intermediate layer.


Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The bit line dielectrics can extend into the semiconductor. The memory cell contains a charge trapping dielectric stack, a poly gate, a pair of pocket implant regions, and a pair of bit lines. The bit line can be formed by an implant process at a higher energy level and/or a higher concentration of dopants without suffering device short channel roll off issues because spacers at bit line sidewalls constrain the implant in narrower implant regions.


Patent
Spansion | Date: 2012-07-31

Systems and methods are provided to minimize write disturb conditions in an untargeted memory cell of a non-volatile memory array. Bitline driver circuits are provided to control a ramped voltage applied both to a bitline of a target memory cell and a neighboring bitline of an untargeted memory cell. Various embodiments advantageously maintain the integrity of data stored in the untargeted memory cells by applying a controlled voltage signal to a previously floating bitline of a neighbor cell to reduce a potential difference between the source and drain nodes of the untargeted neighbor memory cell during a write operation at a target memory cell. In another embodiment, an increased source bias voltage is applied on a source bitline of the target cell during the ramping of the drain bias voltage and then reduced to a ground or near ground potential during the write operation.


Patent
Spansion | Date: 2013-03-18

A method includes minimizing current leaking through a virtual ground pipe during access of NROM memory cells. The minimizing includes operating two neighboring memory cells generally together, which includes connecting an operation voltage to a shared local bit line of the two neighboring memory cells and connecting the external local bit lines of two neighboring memory cells to a receiving unit, such as a ground supply or two sense amplifiers. Also included is an array performing the method.

Discover hidden collaborations