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Solomon, Hong Kong

Lui S.-H.,Solomon Systech Ltd | Kwan H.-K.,University of Hong Kong | Wong N.,University of Hong Kong
International Journal of Circuit Theory and Applications | Year: 2010

We present a framework for synthesizing low-power analog circuits through global optimization over generally nonconvex multivariate polynomial objective function and constraints. Specifically, a nonconvex optimization problem is formed, which is then efficiently solved through convex programming techniques based on linear matrix inequality (LMI) relaxation. The framework allows both polynomial inequality and equality constraints, thereby facilitating more accurate device modelings and parameter tuning. Compared to traditional nonlinear programming (NLP), the proposed methodology exhibits superior computational efficiency, and guarantees convergence to a globally optimal solution. As in other physical design tasks, circuit knowledge and insight are critical for initial problem formulation, while the nonconvex optimization machinery provides a versatile tool and systematic way to locate the optimal parameters meeting design specifications. Two circuit design examples are given, namely, a nested transconductance(Gm)-capacitance compensation (NGCC) amplifier and a delta-sigma (ΔΣ) analog-to-digital converter (ADC), both of them being the key components in many electronic systems. Copyright © 2008 John Wiley & Sons, Ltd. Source


Li R.T.H.,City University of Hong Kong | Chung H.S.-H.,City University of Hong Kong | Lau W.-H.,City University of Hong Kong | Zhou B.,Solomon Systech Ltd
IEEE Transactions on Power Electronics | Year: 2010

Unipolar switching scheme (USS) and bipolar switching scheme (BSS) are popular choices of switching techniques for most inverter applications. Ideally, the output waveform with USS has lower switching loss and harmonic distortion than that with BSS. However, due to the narrow pulses generated around the zero-crossing region, the practical output waveform with USS exhibits pulse-dropping phenomenon that introduces undesirable low-order harmonics. Conversely, BSS does not possess such drawback as the duty cycles of the pulses around the zero-crossing region are close to 0.5. In this paper, a hybrid switching scheme (HSS) that combines the advantages of USS and BSS is proposed and applied to grid-connected current-source inverters. The inverter bridge is predominantly operated in USS and momentarily operated in BSS around the zero-crossing region. A theoretical study shows that the spectral characteristics of HSS are similar to that of an ideal USS. To further reduce the switching loss, the concept of passive resonant snubber is applied to the high-frequency switches in the inverter. The modes of operations, criteria for ensuring soft switching, and design procedures will be addressed in this paper. A 900-W, 220-V, 50-Hz prototype with the HSS and the snubber circuit has been built and tested. A comparative study of the converter efficiencies and total harmonic distortions at the inverter output with different switching schemes will be given. © 2010 IEEEB. Source


Chen J.,Solomon Systech Ltd | Shibata T.,University of Tokyo
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2010

An analog circuit for implementing pulse-coupled neural networks (PCNNs) in very-large-scale integration (VLSI) hardware has been developed using the Neuron-MOS (VMOS) technology. PCNNs are biologically inspired models having powerful ability for image feature generation. With the vMOS technology, weighted sum of multiple input signals, which is an essential of PCNNs, is implemented simply by the capacitive coupling effect in a vMOS block. By employing the switched floating gates in the vMOS blocks as temporary analog memories, the storage of image data is simply realized. Moreover, the function of decay generation, which is crucial for emulating PCNNs neuronal dynamics, is also merged into a vMOS block by utilizing the input-terminal capacitors in it. With such techniques, the circuit achieves a purely voltage-mode implementation of PCNNs in a compact structure. Inheriting the merits of PCNNs, the circuit has good discriminability against different patterns as well as robustness against rotation and translation of identical patterns, which is analogous to human image perception. The performance of the circuit has been verified by the measurements of a proof-of-concept chip fabricated in a 0.35-μm double-polysilicon CMOS technology. © 2010 IEEE. Source


Patent
Solomon Systech Ltd | Date: 2013-08-05

A poly-phase frame modulation system includes a phase matrix look-up table being configured for generating a reference phase matrix; a first phase modulator being configured for generating a first modulated output by taking in the data from a red channel and the sum of the reference phase matrix and a frame offset; a second phase modulator being configured for generating a second modulated output by taking in the data from a green channel and the sum of the reference phase matrix, the frame offset and a first channel offset; and a third phase modulator being configured for generating a third modulated output by taking in the data from a blue channel and the sum of the reference phase matrix, the frame offset and a second channel offset.


A method is provided for recognizing touches by at least a finger on a touch panel and determining positions of the touches by analyzing a change in capacitance of electrodes of the touch panel. The change in capacitance is represented as at least an array. A digital signal processing unit and a touch panel that implement the method are also provided.

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