Santa Clara, CA, United States
Santa Clara, CA, United States
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A method for allocation of a segmented interconnect in an integrate circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. The method also comprises contending for the plurality of resources in accordance with requests from the plurality of resource consumers. Finally, the method comprises accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of global segment buses.


A method for allocation of a shared interconnect structure in an integrated circuit is disclosed. The method comprises receiving a plurality of requests from a plurality of resource consumers of a plurality of engines to access a plurality of resources, wherein the resources are spread across the plurality of engines and contain data for supporting execution of multiple code sequences. The method also comprises contending for the plurality of resources in accordance with requests from the plurality of resource consumers. Finally, the method comprises accessing the plurality of resources via a global interconnect structure, wherein the global interconnect structure has a finite number of buses accessible each clock cycle, and wherein the global interconnect structure comprises a plurality of shared interconnect structures, wherein each shared interconnect structure is shared by each of a sender and each of a receiver.


Patent
Soft Machines | Date: 2016-11-16

A method for converting guest instructions into native instructions is disclosed. The method comprises accessing a guest instruction and performing a first level translation of the guest instruction. The performing comprises: (a) comparing the guest instruction to a plurality of group masks and a plurality of tags stored in multi-level conversion tables by pattern matching subfields of the guest instruction in a hierarchical manner, wherein the conversion tables store mappings of guest instruction bit-fields to corresponding native instruction bit-fields; and (b) responsive to a hit in a conversion table, substituting a bit-field in the guest instruction with a corresponding native equivalent of the bit-field. The method further comprises performing a second level translation of the guest instruction using a second level conversion table and outputting a resulting native instruction when the second level translation proceeds to completion.


A system for an agnostic runtime architecture is disclosed. The system includes a system emulation/virtualization converter, an application code converter, and a system converter wherein the system emulation/virtualization converter and the application code converter implement a system emulation process, and wherein the system converter implements a system conversion process for executing code from a guest image. The system converter further comprises a guest fetch logic component for accessing a plurality of guest instructions, a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling the plurality of guest instructions into a guest instruction block, and a plurality of conversion tables including a first level conversion table and a second level conversion table coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The system further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block. Upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache, and in response to the hit the conversion look aside buffer forwards the translated native instruction for execution.


A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; and determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.


A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks; using a plurality of register templates to track instruction destinations and instruction sources by populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the blocks of instructions; populating a source view data structure, wherein the source view data structure stores sources corresponding to the instruction blocks as recorded by the plurality of register templates; and determining which of the plurality of instruction blocks are ready for dispatch by using the populated source view data structure.


A method for dependency broadcasting through a source organized source view data structure is disclosed. The method comprises receiving an incoming instruction sequence using a global front end and grouping the instructions to form instruction blocks. Further, the method comprises populating the register template with block numbers corresponding to the instruction blocks, wherein the block numbers corresponding to the instruction blocks indicate interdependencies among the instruction blocks wherein an incoming instruction block writes its respective block number into fields of the register template corresponding to destination registers referred to by the incoming instruction block. The method also comprises populating a source organized source view data structure, wherein the source view data structure stores the instruction sources corresponding to the instruction blocks as read from the register template by incoming instruction blocks.


A method for emulating a guest centralized flag architecture by using a native distributed flag architecture. The method includes receiving an incoming instruction sequence using a global front end; grouping the instructions to form instruction blocks, wherein each of the instruction blocks comprise two half blocks; scheduling the instructions of the instruction block to execute in accordance with a scheduler; and using a distributed flag architecture to emulate a centralized flag architecture for the emulation of guest instruction execution.


Methods for read request bypassing a last level cache which interfaces with an external fabric are disclosed. A method includes identifying a read request for a read transaction, generating a phantom read transaction identifier for the read transaction and forwarding said read transaction with said phantom read transaction identifier beyond a last level cache before detection of a hit or miss with respect to said read transaction, and wherein said read transaction is canceled if said read transaction is a hit in said last level cache or does not access said last level cache.


A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.

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