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Coimbatore, India

Meenakumari M.,SNS College Engineering | Sharmila S.,SNS College Engineering
International Journal of Applied Engineering Research

Content addressable memory (CAM) is a memory unit that performs single clock cycle content matching instead of an address. CAMs are vastly used in network routers and cache controllers, as basics look-up table function is performed over all the stored memory information with high power dissipation. There is a trade-off between power consumption, area used and speed. A robust, low power and soaring speed sensing amplifier are requisite after memory design. In this paper, a parity bit is used to reduce the peak and average power consumption and enhance the robustness of the design against process variation. Thus, proposed method is a reordering overlapped mechanism used to reduce power consumption. In this mechanism, the word circuit is split into two sections that are searched sequentially. The main CAM challenges are to reduce power consumption associated with large amount of parallel process, exclusive of sacrificing speed or memory density. © Research India Publications. Source

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