Seoul, South Korea
Seoul, South Korea

SK Hynix Inc. is a South Korean memory semiconductor supplier of dynamic random access memory chips and flash memory chips. Hynix is the world's second-largest memory chipmaker and the world's sixth-largest semiconductor company. Founded as Hyundai Electronic Industrial Co., Ltd. in 1983 and known as Hyundai Electronics, the company has manufacturing sites in Korea, the US, China and Taiwan. In 2012, when SK Telecom became its major shareholder, Hynix merged to SK Group, the third largest conglomerate in South Korea. The company's shares are traded on the Korea Stock Exchange, and the Global Depository shares are listed on the Luxembourg Stock Exchange.Hynix memory is used by Apple Inc. in some of their MacBook and Macbook Pro computers, by Asus in their Google-branded Nexus 7 tablet, is an OEM provider for IBM System x servers, and is used in PC desktops as well as the ASUS Eee PC. Dell and Hewlett-Packard have also used Hynix memory as OEM equipment. Other products which uses Hynix memory include DVD players, cellular phones, set-top boxes, personal digital assistants, networking equipment, and hard disk drives. Wikipedia.


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Patent
Toshiba Corporation and SK hynix | Date: 2016-09-06

According to one embodiment, a magnetic memory includes a first metal layer including a first metal, a second metal layer on the first metal layer, the second metal layer including a second metal which is more easily oxidized than the first metal, the second metal layer having a first sidewall portion which contacts the first metal layer, and the second metal layer having a second sidewall portion above the first sidewall portion, the second sidewall portion which steps back from the first sidewall portion, a magnetoresistive element on the second metal layer, a third metal layer on the magnetoresistive element, and a first material which contacts a sidewall portion of the magnetoresistive element and the second sidewall portion of the second metal layer, the first material including an oxide of the second metal.


Patent
Toshiba Corporation and SK hynix | Date: 2016-09-12

According to one embodiment, there is provided a magnetoresistive element, including a first magnetic layer, a nonmagnetic layer on the first magnetic layer, and a second magnetic layer on the nonmagnetic layer, wherein one of the first and second magnetic layers include one of Co and Fe, and a material having a higher standard electrode potential than Co and Fe.


A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.


Patent
SK hynix | Date: 2016-06-03

A decoder includes a syndrome generator for receiving a codeword and generating at least two syndromes based on the codeword, an error location polynomial generator for generating an error-location polynomial based on the syndromes, an error location determiner for determining at least one error location based on the error-location polynomial, and an error corrector for correcting the codeword based on the one error location. The error location polynomial generator includes a logic for receiving the syndromes and generating a combination of the syndromes as a combination of coefficients of the error-location polynomial, and a key equation solver for generating the error-location polynomial based on the combination of the coefficients and finding at least one root of the error-location polynomial. The error location determiner determines the error location based on a combination of the root and one of the syndromes.


Patent
SK hynix | Date: 2016-08-15

An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.


A method is provided for programming a non-volatile memory having a plurality of word lines, the method comprising: applying a pass voltage to a selected word line among the plurality of word lines; and applying one of first and second program voltages to the selected word line by increasing the pass voltage, wherein the applying of one of the first and second program voltages increases the pass voltage with a single increment.


Patent
SK hynix | Date: 2016-06-06

Memory systems may include a memory including a plurality of wordlines, each wordline including a plurality of cells, and a controller suitable for obtaining an initial voltage threshold and a target state for each of the plurality of cells, applying a pulse based on a pulse value to the plurality of cells, and calculating at least one coupling effect to neighboring cells.


A method of recovering a voltage drop at an output terminal of a voltage compensation circuit connected to a load including a variable load current according to a condition of the load. A circuit portion for a regulator having an output terminal connected to a load including a variable load current may be provided, The circuit portion may include a plurality of stages connected in parallel to said output terminal. Each of said stages may be configured as a current driver having an output connected to the output terminal of said regulator. The circuit portion may include a comparator in each of said stages configured for receiving from a first input a reference voltage value and a predetermined threshold voltage from an other input. Each of said stages may receive a corresponding different threshold voltage value on said other input. The threshold voltage values may be correlated to the variable load current. At least a group of said stages may be sequentially enabled by each corresponding comparator to drive an extra current on said output terminal according to the amount of load current required by the load.


Patent
SK hynix | Date: 2016-07-25

Memory systems may include a logical block address (LBA) space divided into a number of zones, a counter associated with each zone, each counter suitable for incrementing a count value when a read is performed on an LBA in the zone with which the counter is associated, and a controller suitable for calculating a temperature of each zone based on the count values of the counters, sorting the zones according to the calculated temperature, combining the zones into a number of superzones based on the sorting, and splitting the number of superzones into the number of zones into which the LBA space was divided.


Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (BAR) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request.

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