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FOUNTAIN HILLS, AZ, United States

Lepkowski W.,Arizona State University | Ghajar M.R.,Arizona State University | Wilk S.J.,Sjt Micropower Inc | Summers N.,Arizona State University | And 2 more authors.
IEEE Transactions on Electron Devices | Year: 2011

Metalsemiconductor field-effect transistors (MESFETs) have been fabricated using a 150-nm partially depleted silicon-on-insulator complementary metal-oxide-semiconductor (CMOS) technology. Minimum gate lengths of 150 nm have been achieved, which represents a significant reduction compared with an earlier demonstration using a 350-nm CMOS technology. The scaled MESFETs with Lg = 150 nm have a current drive that exceeds 200 mA/mm with a peak fT 35 GHz. This is considerably higher than the Lg = 400 nm MESFET with a current drive of ∼70 mA/mm and a peak fT = 10.6 GHz, which was possible with the earlier generation. However, short-channel effects become significant for Lg < 400 nm, resulting in an optimum MESFET gate length for this technology in the range of 200300 nm. © 2011 IEEE. Source


Grant
Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 625.91K | Year: 2011

We have developed a low dropout (LDO) regulator using a patented MESFET transistor technology that can be manufactured in commercial CMOS foundries with no changes to the process flow. The regulator is stable under all load conditions without an external compensation capacitor, thereby reducing the mass/volume of the power management system and increasing reliability. The MESFET-based LDO component has very competitive figures of merit (dropout voltage, transient response, power supply rejection) compared to existing components. During Phase 1 we confirmed that the components were unconditionally stable without an external compensation capacitor over the temperature range -196C to +150C and for radiation doses up to 1 Mrad(Si). We shall build on the Phase 1 design effort to demonstrate two fully integrated LDO regulators rated up to 1A with dropout voltages of less than 50 mV. One part will be fabricated using a qualified rad-hard SOI CMOS foundry in collaboration with Honeywell, one of our commercialization partners. The other component will be fabricated using the low-cost/high-volume foundry available from IBM. Both parts will have a nominal output voltage of 1.8V with 1% accuracy. Other designs will target user adjustable voltages in the range 1.2-2V. The feasibility of using the MESFET technology for low voltage applications (e.g. 0.8V) will be explored. All parts will be tested over the temperature range -150C to +150C and after irradiation exposure to a TID of 1 Mrad from a Co-60 source. The enhanced low dose rate sensitivity (ELDRS) of the components will be studied using a low dose rate Cs-137 source. The characteristics of all the components will be documented, and parts made available to NASA and potential customers as deliverables from the Phase 2 activity. We shall work with our commercialization partners to have the LDO regulator design adopted as a licensed 'IP block' and to develop low cost versions for the wider consumer electronics market.


Grant
Agency: Department of Defense | Branch: Defense Advanced Research Projects Agency | Program: STTR | Phase: Phase I | Award Amount: 98.97K | Year: 2007

Simulations of high performance silicon-on-insulator (SOI) MESFETs show that they can be used for ultra-low power (ULP) radio frequency electronics with power added efficiencies (PAE) that are 10 times higher than existing solutions. The high PAE comes from the enhanced voltage swing that the MESFETs can tolerate (5-50V) compared to current VLSI CMOS technologies (1-5V). The SOI MESFETs can be fabricated economically using existing SOI CMOS foundries with no changes to the CMOS process flow. This means the SOI MESFETs can be integrated with state-of-the-art CMOS for ULP mixed signal circuit applications, something that is impossible with GaAs based devices. We propose to design an SOI MESFET based Class E amplifier for ULP communications applications in the Industrial-Scientific-Medical band of frequencies. The MESFET based designs will be compared to equivalent CMOS circuits to quantify the anticipated improvement in the PAE of the MESFET circuits. A hardware demonstrator of the Class E amplifier will be designed and tested using existing SOI MESFETs from a previous SBIR contract. Other examples of ULP circuits in which inductive loads lead to device voltages that would cause failure in traditional CMOS will be explored in any Phase II activity.


Grant
Agency: Department of Health and Human Services | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 100.00K | Year: 2007

DESCRIPTION (provided by applicant): This proposal describes the research required to design, simulate and manufacture ultra-low power circuitries to be used in a transmitter implanted inside the human body. Currently, it is difficult to communicate with devices implanted within the human body and the present commercial technologies do not fill this need. We have identified that circuits using SJT Micropower proprietary MESFET technologies will have a lower current draw resulting in longer lifetimes than conventional devices and will be more suited for implanted devices. In order to improve communication with implanted devices, the FCC implemented the Medical Implant Communications Service (MICS) which is an ultra-low power, unlicensed, mobile radio service for transmitting data in support of diagnostic or therapeutic functions associated with implanted medical devices [1]. The FCC rules require that devices operating in the MICS frequency band of 402-405 MHz are limited to a bandwidth of 300kHz and maximum effective isotropic radiated power (EIRP) of 25 microwatts [1]. In preliminary results, we have demonstrated both a novel voltage controlled oscillator operating between 402-405MHz and a low power second stage buffer to drive an antenna. These circuits utilize our patented MESFET transistors, operate with less than 1mA and are the backbone circuitry of a transmitter. SJT Micropower already has microfabricated MESFETs from other process runs on hand and they will be used for a prototype hardware demonstration. The main project objectives are to: Objective 1) Design and simulate an ultra-low power voltage controlled oscillator (VCO) and a high efficiency output buffer using Cadence Design Software. Objective 2) Integrate the VCO and buffer together and optimize for ultra-low power operation and reliability using Cadence Design Software. Objective 3) Microfabrication layout of individual and integrated circuit components using Cadence CAD software tools to extract parasitics and optimize design. Objective 4) Build, characterize and document a hardware demonstration VCO and second stage buffer integrated together using pre-fabricated MESFETs. Our long-term goal is a fully integrated transceiver designed for operation in accordance with the MICS regulations. This device will be implanted within the human body and will improve patients' quality of life. The specific aims of this project will be to provide the circuit components necessary for the transmitter portion of the MICS transceiver. 7. Project Narrative currently, it is very difficult for medical devices implanted within the human body to communicate with medical professionals in the outside world. This research will utilize the Medical Implant Communications Service (MICS) to build novel components for a low power transceiver which will allow physicians the ability to use wireless technology to diagnose and treat their patients. The final devices will permit faster data transfer rates between medical implants and external monitoring/control equipment, reduce the risk of infection to patients, enhance the comfort of patients, and expand the freedom of movement of medical personnel working with the equipment [2].


Grant
Agency: Department of Defense | Branch: Defense Advanced Research Projects Agency | Program: STTR | Phase: Phase II | Award Amount: 730.63K | Year: 2010

Voltage compliant metal-semiconductor field-effect-transistors (MESFETs) provide solutions to critical problems arising from the reduced operating voltage of highly scaled CMOS. This Phase 2 activity will develop MESFET based circuitries that allow high voltage applications to coexist on future, highly scaled low voltage CMOS applications. Our patented MESFET technology will be used to develop both RF and DC applications with a focus on RF power conversion, DC power management and driver applications. Our first objective is to develop high efficiency power amplifiers (PAs) for ultra-low power RF transceivers. As the supply voltage is reduced, resistive losses in the power amplifier limit its overall RF power conversion efficiency. Phase 2 will demonstrate a fully integrated PA module for system-on-a-chip transceiver applications that take advantage of the MESFETs high voltage capability to eliminate these problems. The second objective is to demonstrate low dropout (LDO) linear regulators for RF transceivers. The MESFET LDOs will have greater load stability, smaller silicon area and faster settling time compared to existing p-channel CMOS designs. We shall partner with Honeywell and Jazz Semiconductor during Phase 2 to demonstrate the MESFET circuits using advanced SOI CMOS technologies. These collaborations will be further developed for Phase 3 Commercialization activities.

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