Entity

Time filter

Source Type

Chittoor, India

Sreeranganayakulu J.,SITAMS | Marutheswar G.V.,Sri Venkateswara University | Anjaneyulu K.S.R.,Jawaharlal Nehru Technological University Anantapur
International Journal of Control Theory and Applications | Year: 2015

Subsynchronous Resonance (SSR) is a serious problem due to series capacitor placement in power system networks which causes uncontrolled oscillations in the mechanical system of a multi mass model [1]. Many models have been developed to mitigate these oscillations which generally occur during a three phase fault on the power system. In this paper IEEE second benchmark system [2] is investigated using MATLAB based on the Power System Block-set (PSB) in conjunction with Simulink. Here, this model is simulated without FACTS controllers and then the Static Synchronous Series Compensator (SSSC) is included in the model and the results are compared for their effectiveness in damping the SSR oscillations. © International Sciences Press, India. Source


Sarvabhatla M.,NBKRIST | Narayana K.L.,SITAMS | Vorugunti C.S.,Dhirubhai Ambani Institute of ICT
2015 IEEE International Conference on Signal Processing, Informatics, Communication and Energy Systems, SPICES 2015 | Year: 2015

The advancement of communication technology resulted in increasing number of security threats over public Internet on remote servers. In 2014, Shipra et al. proposed an improved remote user authentication scheme using smart cards with check digits. Shipra et al. claimed that their scheme is secure and efficient against all major cryptographic attacks. Unfortunately, their scheme is vulnerable to some of the cryptographic attacks, particularly 'online password guess attack' as discussed in this manuscript. As a part of our contribution, we propose a robust and extra secure authentication scheme for remote users based on smart cards with check digits, with slight increase in the cost. Security is the fundamental compared to complexity, since complexity can be easily manage with improved technology. © 2015 IEEE. Source


Gundala S.,SITAMS | Ramanaiah V.K.,Yogi Vemana University | Kesari P.,JNTUA
Research Journal of Applied Sciences, Engineering and Technology | Year: 2015

The level shifters play a crucial role in multi supply systems and it is the effective way to reduce the power consumption at system level. The level shifters are the interfacing circuits, used to interface multi supply voltage modules. The design and analysis of competent level shifter is described in this study, with a lower energy and delay constraints. It is a novel architecture with multiplexer based circuit to perform both levels-up and levels-down operations. Proposed level shifter circuit has designed and analyzed using 90 nm CMOS process technology. This proposed level shifter can be operated at different supply voltages from 0.3 to 0.5 V of VDDL and 0.9 to 1.1V of VDDH. The experimental and simulation results exhibits that the proposed circuit is having levels-up and levels-down average power is 17.57 nW and delay is 1.49 ns at a simulated frequency of 1 MHz. The level shifter has designed and simulated with different load and operating conditions. The proposed competent level shifter circuit is suitable for low power and high speed applications. © Maxwell Scientific Organization, 2015. Source


Gundala S.,SITAMS | Ramanaiah V.K.,Yogi Vemana University | Kesari P.,JNTUK UCE
2014 International Conference on Advances in Electronics, Computers and Communications, ICAECC 2014 | Year: 2015

The power consumption is a major concern for emerging applications like mobile phones, digital cameras, pace makers and multimedia processors. The power consumption can decreases by number of ways. The multiple supply voltage design is a dominant technique for the reduction of power consumption in System on Chips/Cores. The System on Chips/Cores uses level shifters and the level shifter will become overhead, when its own power consumption & delay is high. In this paper a nanosecond delay level Shifter with logic level correction circuit is introduced that performs level up shifting as well as logic level correction to keep the VOUT stable, equals to VDD or VSS with low power consumption. The circuit is designed and simulated in a 90nm process technology. The proposed technique is a unique component, will comprise a feedback network to keep the output as stable as possible. Robustness of the new level shifter design has examined at an operating frequencies of 10 KHz, 500 KHz, and 1 MHz with varying load of 10 fF to 70 fF and varying temperature from-20 °C to 70 °C. The proposed design reliably shifts 0.4V input signal to 1V output signal with a delay as low as 0.8ns and average power consumption of 80nW at a frequency of 1MHz. © 2014 IEEE. Source


Gundala S.,SITAMS | Ramanaiah V.K.,Yogi Vemana University | Padmapriya K.,JNTUK UCE
ARPN Journal of Engineering and Applied Sciences | Year: 2015

Level shifters are interfacing circuits, generally for Low voltage to high voltage translation Level shifters are used and high to low translation inverters are sufficient, but it needs an additional circuitry. In this paper we have presented a novel high performance Dynamic Voltage Level Shifter. It is a unique circuit will perform level-up shift, level-down shift, and Blocking. The type of shift, Level up/down is will be performed automatically based on its input voltage (VIN). The proposed dynamic voltage level shifter has designed and simulated in 90nm technology. Simulation results demonstrate that the proposed level shifter translates voltages between 0.4V to 1V and vice versa, at operating frequencies of 100 KHz, 500 KHz, and 1 MHz. It is observed that the proposed design having static power of 4.6 nW while level up, and 2.8 nW while level down operations. Level up and level down average active power is 20.9 nW. © 2006-2015 Asian Research Publishing Network (ARPN). Source

Discover hidden collaborations