Udaipur, India

Sir Padampat Singhania University is a private residential university located in Udaipur, India. The university offers undergraduate and graduate degree programs in engineering. It has a management school that offers Master of Business Administration degrees. The university was established in 2008, and its pioneering batch of students graduated in 2011.It is named after the noted Indian industrialist and member of the Indian constituent assembly, Sir Padampat Singhania. Wikipedia.


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Pareek N.K.,University Computer Center | Patidar V.,Banasthali University | Sud K.K.,Sir Padampat Singhania University
International Journal of Network Security | Year: 2010

Chaotic systems have many interesting features such as sensitivity on initial condition and system parameter, ergodicity and mixing properties. In this paper, we exploit these interesting properties of chaotic systems to design a random bit generator, called CCCBG, in which two chaotic systems are cross-coupled with each other. To evaluate the randomness of the bit streams generated by the CCCBG, the four basic tests: monobit test, serial test, auto-correlation, Poker test and the most stringent tests of randomness: the NIST suite tests have been performed. As a result no patterns have been observed in the bit streams generated by the proposed CCCBG. The proposed CCCBG can be used in many applications requiring random binary sequences and also in the design of secure cryptosystems.


Raghuwanshi S.K.,Sir Padampat Singhania University | Raghuwanshi S.K.,Indian School of Mines
Indian Journal of Physics | Year: 2010

In this paper we have studied the asymmetric versus symmetric planar waveguide in terms of their usefulness in optical fiber communication systems. We have explored the thin waveguide versus thick waveguide first. Later on usefulness of asymmetric versus symmetric waveguide is carried out to target for WDM optical network application. All kinds of optical network components are fabricated on Si substrate with the point of view of their application. Here asymmetric planar structure may be more useful compared to symmetric waveguide in terms of their non-uniform power confinement properties. However, the symmetric waveguide structure may be more useful for their high power confinement properties. It is well known that the thin symmetric waveguide supports at least one mode. However the thick waveguide may support many even as well as odd modes. We study the power confinement properties for symmetric as well as asymmetric waveguide structure. We conclude that higher order modes show the nonlinear power variations. Mode field profile for various cases is discussed as well. Comparative study between asymmetric versus symmetric waveguide has a lot of significance in optical network area. It has been shown through analysis that in asymmetric waveguide, the power flows more through film region in the case of fundamental mode. Power confinement properties for asymmetric waveguide versus symmetric waveguide have been studied. © 2010 IACS.


Patidar V.,Sir Padampat Singhania University | Pareek N.K.,University of Rajasthan | Purohit G.,Sir Padampat Singhania University | Sud K.K.,Sir Padampat Singhania University
Optics Communications | Year: 2011

A novel and robust chaos-based pseudorandom permutation-substitution scheme for image encryption is proposed. It is a loss-less symmetric block cipher and specifically designed for the color images but may also be used for the gray scale images. A secret key of 161-bit, comprising of the initial conditions and system parameter of the chaotic map (the standard map), number of iterations and number of rounds, is used in the algorithm. The whole encryption process is the sequential execution of a preliminary permutation and a fix number of rounds (as specified in the secret key) of substitution and main permutation of the 2D matrix obtained from the 3D image matrix. To increase the speed of encryption all three processes: preliminary permutation, substitution and main permutation are done row-by-row and column-by-column instead of pixel-by-pixel. All the permutation processes are made dependent on the input image matrix and controlled through the pseudo random number sequences (PRNS) generated from the discretization of chaotic standard map which result in both key sensitivity and plaintext sensitivity. However each substitution process is initiated with the initial vectors (different for rows and columns) generated using the secret key and chaotic standard map and then the properties of rows and column pixels of input matrix are mixed with the PRNS generated from the standard map. The security and performance analysis of the proposed image encryption has been performed using the histograms, correlation coefficients, information entropy, key sensitivity analysis, differential analysis, key space analysis, encryption/decryption rate analysis etc. Results suggest that the proposed image encryption technique is robust and secure and can be used for the secure image and video communication applications. © 2011 Elsevier B.V.


Pradhan A.,Hindu Post Graduate College | Chouhan D.S.,Sir Padampat Singhania University
Astrophysics and Space Science | Year: 2010

The present study deals with a spatially homogeneous and anisotropic Bianchi-I cosmological models representing massive strings. The energy-momentum tensor, as formulated by Letelier (1983), has been used to construct massive string cosmological models for which we assume the expansion scalar in the models is proportional to one of the components of shear tensor. The Einstein's field equations have been solved by applying a variation law for generalized Hubble's parameter in Bianchi-I space-time.We have analysed a comparative study of accelerating and decelerating models in the presence of string scenario. The study reveals that massive strings dominate in the decelerating universe whereas strings dominate in the accelerating universe. The strings eventually disappear from the universe for sufficiently large times, which is in agreement with current astronomical observations. © Springer Science+Business Media B.V. 2010.


Pradhan A.,Hindu Post graduate College | Kumar Singh A.,Hindu Post graduate College | Chouhan D.S.,Sir Padampat Singhania University
International Journal of Theoretical Physics | Year: 2013

In this paper we discuss the law of variation of scale factor a=(tket)1/n which yields a time-dependent deceleration parameter (DP) representing a new class of models that generate a transition of universe from the early decelerated phase to the recent accelerating phase. Exact solutions of Einstein's modified field equations in Bianchi type-V space-time with perfect fluid and heat conduction are obtained within the framework of Sáez-Ballester scalar-tensor theory of gravitation and the model is found to be in good agreement with recent observations. We find, for n=3,k=1, the present value of DP in derived model as q0=-0. 67 which is very near to the observed value of DP at present epoch. We find that the time-dependent DP is sensible for the present day Universe and give an earmark description of evolution of universe. Some physical and geometric properties of the models are also discussed. © 2012 Springer Science+Business Media, LLC.


Pareek N.K.,University Computer Center | Patidar V.,Sir Padampat Singhania University | Sud K.K.,Sir Padampat Singhania University
Digital Signal Processing: A Review Journal | Year: 2013

In this paper, an encryption algorithm for gray images using a secret key of 128-bits size is proposed. Initially, visual quality of image is degraded by the mixing process. Resultant image is partitioned into key dependent dynamic blocks and, further, these blocks are passed through key dependent diffusion and substitution processes. Total sixteen rounds are used in the encryption algorithm. Proposed technique is simple to implement and has high encryption rate. Simulation experiment results have been given to validate the high security features and effectiveness of proposed system. © 2013 Elsevier Inc.


Singh A.,SGVU | Chakrabarti P.,Sir Padampat Singhania University
Proceedings of the 2013 3rd IEEE International Advance Computing Conference, IACC 2013 | Year: 2013

In Mobile Grid systems, the automatic service deployment initially requires the node discovery. Most of the existing security mechanisms on Grid systems rarely consider the mobility of the nodes which may affect the applied security mechanisms leading to insufficient and inaccurate security. In order to overcome these issues, in this paper, we propose an ant based resource discovery and mobility aware trust management for mobile grid systems. Initially the super-grid nodes are selected in the network using ant colony optimization based on the parameters such as distance, CPU speed, available bandwidth and residual battery power. These selected nodes are utilized in the resource discovery mechanism. In order to maintain strong security with mobility management system, a proficient trust reputation collection method has been adopted. By simulation results, we show that the proposed approach is efficient and offers more security. © 2013 IEEE.


Gupta N.,Sir Padampat Singhania University
Proceedings - 2014 6th International Conference on Computational Intelligence and Communication Networks, CICN 2014 | Year: 2014

This paper, deals with Latch Free Clock Gating technique for reduction of clock power and total power consumption in Low Power Arithmetic and Logic Unit and we have analysed power reduction on different FPGA devices. Without latch free clock gating technique in Low Power Arithmetic and Logic Unit the Contribution of Clock power was 39mW in Virtex-6 FPGA, 14mW in Virtex-5 FPGA, 24mW in Virtex-4 FPGA, 18mW in Spartan-3 FPGA, 18mW in Spartan-3E FPGA, 18mW in Spartan-6 FPGA, 5mW in Artix-7 FPGA of total power when device is operating at frequency of 1GHz. After implementation of latch free clock gating technique in Low Power Arithmetic and Logic Unit, Clock power contribution is 3mW in Virtex-6 FPGA, 5mW in Virtex-5 FPGA, 8mW in Virtex-4 FPGA, 5mW in Spartan-3 FPGA, 9mW in Spartan-3E FPGA, 7mW in Spartan-6 FPGA, 2mW in Artix-7 FPGA in total power. Total Power consumption is reduces to 1.41%, 1.33%, 2.53%, 7.65%, 2.88%, 3.38% and 2.64% on 40-nm Virtex-6, 65-nm Virtex-5, 90-nm Virtex-4, Spartan 3, Spartan 3E, Spartan-6 and Artix-7 target device respectively with device operating frequency is 1GHz. There is 92.31%, 64.29%, 66.67%, 72.22%, 50%, 61.11% and 60% reduction in clock power on 40-nm Virtex-6, 65-nm Virtex-5, 90-nm Virtex 4, Spartan 3, Spartan 3E, Spartan-6 and Artix-7 target device respectively with device operating frequency is 1GHz. © 2014 IEEE.


Purohit G.,Sir Padampat Singhania University | Patidar V.,Sir Padampat Singhania University | Sud K.K.,Sir Padampat Singhania University
Physics Letters, Section A: General, Atomic and Solid State Physics | Year: 2010

We report the results of our modified distorted wave Born approximation calculation of triple differential cross section in the coplanar symmetric single ionization of potassium atom. We have included correlation-polarization potential as a function of electron density parameter and also studied the effect of post-collision interaction. The present attempt significantly improves the agreement between theoretical and experimental results. © 2010 Elsevier B.V. All rights reserved.


Gupta N.,Sir Padampat Singhania University
2014 International Conference on Control, Instrumentation, Communication and Computational Technologies, ICCICCT 2014 | Year: 2014

This paper, deals with Thermal Analysis of Energy Ef ficient Clock Gated Arithmetic Logic Unit on FPGA for reduction of leakage power and total power consumption and it has been analyzed that there is reduction in Leakage Power when ambient temperature decreases from 50 degree Celsius to 20 degree Celsius. Virtex-6 is 40-nm FPGA, on which Thermal Analysis of Energy Efficient Clock Gated Arithmetic Logic Unit has been analyzed with device operating frequency is 1GHz. This reduction in leakage power is analyzed on arithmetic and logic unit with latch free clock gating technique and on arithmetic and logic unit with latch based clock gating technique. There is significant Leakage power reduction by varying ambient temperature. With Latch free clock gating technique in Low Power Arithmetic and Logic Unit the Contribution of leakage power was 1.327W, when Ambient Temperature is 50 degree Celsius, which is further reduced to 1.246W at 40 degree Celsius Ambient Temperature, 1.176W at 30 degree Celsius Ambient Temperature, 1.114W at 20 degree Celsius Ambient Temperature. With Latch based clock gating technique in Low Power Arithmetic and Logic Unit the Contribution of leakage power was 1.328W When Ambient Temperature is 50 degree Celsius, which is further reduced to 1.247W at 40 degree Celsius Ambient Temperature, 1.177W at 30 degree Celsius Ambient Temperature, 1.115W at 30 degree Celsius Ambient Temperature. So, there is reduction in leakage power in energy efficient arithmetic and logic unit. © 2014 IEEE.

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