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Hatkar A.P.,Sir Visvesvaraya Institute of Technology | Hatkar A.A.,Sir Visvesvaraya Institute of Technology
Proceedings - International Conference on Electronic Systems, Signal Processing, and Computing Technologies, ICESC 2014

Reversible logic is very much in demand for the future computing technologies as they are known to produce low power dissipation having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Adders and multipliers are fundamental building blocks in many computational units. In this paper we have presented and implemented reversible Wallace signed multiplier circuit in ASIC through modified Baugh-Wooley approach using standard reversible logic gates/cells, based on complementary pass-transistor logic and have been validated with simulations, a layout vs. Schematic check, and a design rule check. It is proved that the proposed multiplier is better and optimized, compared to its existing counterparts with respect to the number of gates, constant inputs, garbage outputs, hardware complexity, and number of transistors required. It has also been shown in Cadence's tools that the reversible multiplier outperform the irreversible multiplier in terms of power dissipation. © 2014 IEEE. Source

Lambture V.,Sir Visvesvaraya Institute of Technology | Gite B.,Sinhgad Academy of Engineering
ICCRD2011 - 2011 3rd International Conference on Computer Research and Development

In this paper, successfully we had implemented Fant's resampling algorithm by using cubic convolution for resampling the images that consists two passes. It does not exhibit the aliasing artifacts associated with techniques for spatial transform of discrete sampled images is possible through the use of a complete and continuous resampling interpolation algorithm. Applications to image processing include reconstruction, smoothing, enlargement and reduction. © 2011 IEEE. Source

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