Siltronic AG | Date: 2017-08-23
FZ silicon, annealed at an annealing temperature of greater than or equal to 900C, wherein the FZ silicon shows no degradation of its minority carrier lifetime after any processing steps at a processing temperature of less than 900 C. Method to prepare FZ silicon, comprising annealing the FZ silicon at an annealing temperature of greater than or equal to 900C and processing the annealed FZ silicon at a processing temperature of less than 900 C.
Siltronic AG | Date: 2016-09-09
A semiconductor wafer processing susceptor for holding a wafer having an orientation notch during deposition of a layer on the wafer, having a placement surface for supporting the semiconductor wafer in the rear edge region of the wafer, the placement surface having a stepped outer delimitation, and an indentation of the outer delimitation of the placement surface for placement of the partial region of the edge region of the rear side of the wafer in which the orientation notch is located onto a partial region of the placement surface delimited by the indentation of the outer delimitation of the placement surface. The susceptor is used in a method for depositing a layer on a wafer having an orientation notch, and wafers made of monocrystalline silicon upon which layers are deposited using the susceptor have greater local flatness on both front and rear sides proximate the orientation notch.
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 87.61M | Year: 2015
The key objective of PowerBase Enhanced substrates and GaN pilot lines enabling compact power applications is to ensure the availability of Electronic Components and Systems (ECS) for key markets and for addressing societal challenges, aiming at keeping Europe at the forefront of the technology development, bridging the gap between research and exploitation, creating economic and employment growth in the European Union. The project PowerBase aims to contribute to the industrial ambition of value creation in Europe and fully supports this vision by addressing key topics of ECSEL multi annual strategic plan 2014. By positioning PowerBase as innovation action a clear focus on exploitation of the expected result is primary goal. To expand the limits in current power semiconductor technologies the project focuses on setting up a qualified wide band gap GaN technology Pilot line, on expanding the limits of todays silicon based substrate materials for power semiconductors, improving manufacturing efficiency by innovative automation, setting up of a GaN compatible chip embedding pilot line and demonstrating innovation potential in leading compact power application domains. PowerBase is a project proposal with a vertical supply chain involved with contributions from partners in 7 European countries. This spans expertise from raw material research, process innovation, pilot line, assembly innovation and pilot line up to various application domains representing enhanced smart systems. The supporting partners consist of market leaders in their domain, having excellent technological background, which are fully committed to achieve the very challenging project goals. The project PowerBase aims to have significant impact on mart regions. High tech jobs in the area of semiconductor technologies and micro/nano electronics in general are expressed core competences of the regions Austria: Carinthia, Styria, Germany: Sachsen, Bavaria and many other countries/ regions involved.
Agency: European Commission | Branch: H2020 | Program: ECSEL-IA | Phase: ECSEL-02-2014 | Award Amount: 139.30M | Year: 2015
The proposed pilot line project WAYTOGO FAST objective is to leverage Europe leadership in Fully Depleted Silicon on Insulator technology (FDSOI) so as to compete in leading edge technology at node 14nm and beyond preparing as well the following node transistor architecture. Europe is at the root of this breakthrough technology in More Moore law. The project aims at establishing a distributed pilot line between 2 companies: - Soitec for the fabrication of advanced engineered substrates (UTBB: Ultra Thin Body and BOx (buried oxide)) without and with strained silicon top film. - STMicroelectronics for the development and industrialization of state of the art FDSOI technology platform at 14nm and beyond with an industry competitive Power-Performance-Area-Cost (PPAC) trade-off. The project represents the first phase of a 2 phase program aiming at establishing a 10nm FDSOI technology for 2018-19. A strong added value network is created across this project to enhance a competitive European value chain on a European breakthrough and prepare next big wave of electronic devices. The consortium gathers a large group of partners: academics/institutes, equipment and substrate providers, semiconductor companies, a foundry, EDA providers, IP providers, fabless design houses, and a system manufacturer. E&M will contribute to the objective of installing a pilot line capable of manufacturing both advanced SOI substrates and FDSOI CMOS integrated circuits at 14nm and beyond. Design houses and electronics system manufacturer will provide demonstrator and enabling IP, to spread the FDSOI technology and establish it as a standard in term of leading edge energy efficient CMOS technology for a wide range of applications battery operated (consumer , healthcare, Internet of things) or not. Close collaboration between the design activities and the technology definition will tailor the PPAC trade-off of the next generation of technology to the applications needs.
Agency: European Commission | Branch: H2020 | Program: ECSEL-RIA | Phase: ECSEL-01-2015 | Award Amount: 33.04M | Year: 2015
The REFERENCE project aims to leverage a European leading edge Radio Frequency (RF) ecosystem based on RF Silicon On Insulator (SOI) disruptive technology, perceived as the most promising to address performance, cost and integration needs for RF Front End Modules (FEMs)s. The project targets to develop over the next 3 years, innovative solutions from material, engineered substrates, process, design, metrology to system integration capable to address the unresolved 4G\ requirements for RF FEMs (data rate >1Gb/s) and pave the way to 5G. The R&D and demonstration actions include: Development of innovative RFSOI substrates for 4G\ / 5G Move to 300 mm diameter Development of 4G\ / 5G RF-SOI devices with 2 major European foundries : analog in 200 mm 130nm technology, RF digital by combining RFSOI and FDSOI in 300 mm at 22nm; Innovative design for 4G\ /5G (analog and RF digital), Integration of several 4G\ FEM components on the same chip and demonstration System in Package Technology (SiP). 3 applications are investigated : Cellular / Iot : 4G\ RFSOI FEM demonstrator at SiP device level Automotive : 4G\ RF-SOI demonstrator at SiP device level Aviation: RF-SOI high data rate wireless communication module at system level; targeting a new frequency band for aeronautic. The project is executed within 5 European countries, by on a strong and complementary and well balanced consortium, 6 large industrial companies (world leaders in material, foundries, aeronautics), 4 SMEs and a network of world class level and major European public research institutes and academics. It clearly aims to develop industrial solutions enabling European leadership and production. Through this technology disruption, REFERENCE project addresses major thrusts for smart mobility, smart society, semiconductor processes, equipments, design technology and smart systems implementation, and support the societal challenges of smart transport, as well as secure and innovative society.
Siltronic AG | Date: 2016-08-03
The present invention relates to a semiconductor wafer (10) comprising a monocrystalline substrate wafer (1) consisting essentially of silicon, the monocrystalline substrate wafer (1) being structured to have tips (3) on its top surface, each of the tips (3) being covered in the given order with a group-IIIB silicide layer (5) and a group-IIIB nitride layer (6), the group-IIIB nitride layer (6) being covered with a monocrystalline group-IIIA nitride layer (7, 8), especially a In_(x)Al_(z)Ga_(1-(x+z))N layer with 0 x, z, (x+z) 1.
Siltronic AG | Date: 2015-11-05
The invention relates to a semiconductor wafer of monocrystalline silicon, and to a method for producing it. The semiconductor wafer has a zone, DZ, which is free of BMD defects and extends from a front side of the semiconductor wafer into the bulk of the semiconductor wafer, and a region having BMD defects which extends from the DZ further into the bulk of the semiconductor wafer. A silicon single crystal is pulled by the Czochralski method and processed to form a polished monocrystalline silicon substrate wafer. The substrate wafer is treated by rapidly heating and cooling the substrate wafer, slowly heating the rapidly heated and cooled substrate wafer, and keeping the substrate wafer at a specific temperature and over a specific period.
Siltronic AG | Date: 2015-11-03
A cleaning method involves: disposing in a cleaning liquid held in a cleaning tank an object to be cleaned; and ultrasonically vibrating the cleaning liquid via an intermediate medium in contact with the cleaning tank to clean said object, the ultrasonically vibrating involving: ultrasonically vibrating the cleaning liquid with the cleaning liquid and the intermediate medium allowing sonic velocities, respectively, having a first difference; and ultrasonically vibrating the cleaning liquid with the cleaning liquid and the intermediate medium allowing sonic velocities, respectively, having a second difference different from the first difference
Siltronic AG | Date: 2016-01-13
A method dresses one polishing cloth or two polishing pads simultaneously, in which a polishing cloth has been applied to a polishing plate, with at least one dresser (4), which is equipped with at least one dressing element (8), this at least one dressing element (8) being in contact with the at least one polishing cloth (11, 12) to be dressed, wherein the at least one polishing plate (21, 22) is rotated with a relative rotational speed and the at least one dresser (4) is rotated with a relative rotational speed and at least two different combinations of directions of rotation of the two pairs of polishing plates (21, 22) and pin wheels (31, 32) are executed during the simultaneous dressing of two polishing pads (11, 12) or during the dressing of one polishing cloth (11) of the polishing plate (21) and of the at least one dresser (4).
Siltronic AG | Date: 2016-04-25
A cleaning method for cleaning an object involves disposing the object in a first cleaning liquid held in a first cleaning tank; ultrasonically vibrating the first cleaning liquid via a first intermediate medium in contact with the first cleaning tank; disposing the object in a second cleaning liquid held in a second cleaning tank; and ultrasonically vibrating the second cleaning liquid via a second intermediate medium in contact with the second cleaning tank, wherein the first cleaning liquid and the first intermediate medium allow sonic velocities, respectively, having a first difference from each other, wherein the second cleaning liquid and the second intermediate medium allow sonic velocities, respectively, having a second difference from each other, and wherein the first and second differences are different from each other.