Silterra Malaysia Sdn. Bhd

Kulim, Malaysia

Silterra Malaysia Sdn. Bhd

Kulim, Malaysia

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Hashim Z.S.,University Technical Malaysia Melaka | Rahman M.N.A.,University Technical Malaysia Melaka | Muhamad M.R.,University Technical Malaysia Melaka | Ahmad A.F.,Silterra Malaysia Sdn. Bhd.
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2016

Copper metallization process, using electroplating, in Integrated Circuit interconnect, poses big challenge in semiconductor fabrication. Besides the stringent Dual Damascene requirement, the copper material itself is prone to rapid interface diffusion as well as surface oxidation. Thus the copper metallization process has to be performed within specific time after copper seed deposition process. This study investigated the impact of bilayer TaN/Ta barrier on copper sheet resistance changes at different time intervals. The study was based on 200mm wafer. In addition to that, correlation between sheet resistance to other copper film properties such as reflectance and stress was also investigated. Based on results of this study, bilayer TaN/Ta barrier inclusion in copper seed greatly improved film sheet resistance stability. © 2016 IEEE.


Bee X.E.,Silterra Malaysia Sdn. Bhd. | Fauzi M.M.B.M.,Silterra Malaysia Sdn. Bhd. | Tan P.B.Y.,Silterra Malaysia Sdn. Bhd.
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2016

In this paper, we propose a methodology to model the MOSFET subthreshold swing, S mismatch by using BSIM4 model. The 0.18μm CMOS technology silicon data show two trends in the swing mismatch plot. For large-size devices (larger than a critical area AC), the subthreshold swing behaves in a linear trend with smaller slope compared to small-size devices. A mathematical equation as a function of AC is added into the BSIM4 subthreshold swing parameter, nfactor to capture the subthreshold swing mismatch correctly. The mismatch models generated using the proposed methodology shows good agreement with the silicon data and has been tested compatible with HSPICE and SPECTRE simulators. © 2016 IEEE.


Tan C.C.,Silterra Malaysia Sdn. Bhd. | Tan P.B.Y.,Silterra Malaysia Sdn. Bhd.
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2016

In this paper, we studied the effect of mechanical stress due to Shallow Trench Isolation (STI) on the channel length direction (x-stress) and channel width direction (y-stress) by adopting two different channel orientations; <110> and <100>. When change from <110> to <100> channel orientation, PMOS sensitivity to both STI x-stress and y-stress reduces. For NMOS, both the channel orientations show the similar STI x-stress and y-stress effects. STI x-stress effects of NMOS and PMOS is contradicting. Hence, by adopting <100> channel, the performance of PMOS can be improved without degrading the NMOS performance. The STI x-stress and y-stress effects on NMOS and PMOS transistors with <110> and <100> channel orientation are explained by using the electron and hole energy valleys diagrams. © 2016 IEEE.


Tan C.C.,Silterra Malaysia Sdn. Bhd. | Tan P.B.Y.,Silterra Malaysia Sdn. Bhd.
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2016

An accurate BSIM4 parameter extraction with Binning-Hybrid-Macro (BHM) methodology has been developed for MOS transistor models. The basic idea of this method is to apply binning on a hybrid-macro model. The comparison between the BHM method and various model extraction methods is discussed. BHM method is more robust and easier to use besides its capability to produce more accurate roll-off fittings compared to other methods. The BHM extraction methodology has been demonstrated on actual silicon from 0.18μm CMOS technology. Accurate model fitting to the measured data has been achieved. The model extracted using BHM method has been tested and verified to be compatible with HSPICE and SPECTRE simulators. © 2016 IEEE.


Abdul Wahab Y.,University of Malaya | Ahmad A.F.,Silterra Malaysia Sdn. Bhd. | Hussin H.,University of Malaya | Hussin H.,University Technology of MARA | Soin N.,University of Malaya
Microelectronics Reliability | Year: 2012

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to mechanical stress in passivated interconnect lines. These mechanisms play a collective role for intensive research of thermal stability for Cu interconnects reliability in CMOS technologies. This paper presents capabilities and performance on samples annealed using furnace vs He in situ anneal and in-line technique developed to reduce total defect count. © 2012 Elsevier Ltd. All rights reserved.


Rahim S.R.A.,University of Tenaga Nasional | Ahmad I.,University of Tenaga Nasional | Chik M.A.,Silterra Malaysia Sdn. Bhd
2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings | Year: 2012

Cycle time for a product is one of the key performance indicators in semiconductor manufacturing. Reduction of cycle time will shorten product time to market, increase throughput, reduce operational cost and develop customer trust. Semiconductor manufacturing that process 40,000 to 50,000 work-in-progresses (WIP), usually takes 50 to 70 days, 300 to 400 equipments and 300 to 900 steps to complete. Thus, any task related to manual data collection to make indices reports or analysis usually needs high resources requirements to spend for manual work and risk for mistake. In the modern facility of semiconductor fabrication, a system like Manufacturing Execution Systems (MES) was implemented to ease the process and operation traceability. The information is well kept in the appropriate databases. Many applications then are integrated with MES database to perform indices reports. In this paper, the improve method for data collection related to cycle time improvement is introduced. In this approach, the automated systems was developed using existing Advance Productivity Family (APF) programming platform to collecting the data. The system is integrated between MES and APF to have the real time data collection and analysis. In the systems, manual data collection is replaced with respective automated data transfer from real situation in the manufacturing environment. This program then able to shows real root caused with proper relational charting to display real problem for engineering to prioritize and resolve respectively. As a result, 39% reduction of cycle time gained by implementing this technique. The system has successfully implemented and supports the cycle time reduction. © 2012 IEEE.


Ibrahim K.,Silterra Malaysia Sdn Bhd | Chik M.A.,Silterra Malaysia Sdn Bhd | Hashim U.,University Malaysia Perlis
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2014

Semiconductor wafer manufacturing, being one of the most advanced and complex process, commands high level of utilization of the available tools to ensure maximum productivity. It is also very important to keep the operations as lean as possible to ensure cost effectiveness. In this research we will show that the cost additional capacity is outrages. This is the main reason more and more companies are opting out of fab owners club. Others are scaling down and going fables and fab-light. Capacity utilization and capacity maximization is the key to a successful fab. Fabs continuously look for ways to increase the capacity by improving productivity. Beyond certain productivity level, fabs must spend on purchasing tools. Semiconductor tools are expensive and in many cases there will be a need to spend in the support infrastructure. The escalating cost really brings out the creativity and innovation among the fab engineers. This paper discusses what actions are taken to address or mitigate this issue. The research is based on some available data from SilTerra Malaysia S dn Bhd wafer fab in Kulim. © 2014 IEEE.


Patent
Silterra Malaysia Sdn. Bhd. | Date: 2012-12-28

A method for manufacturing a planarised reflective layer disposed on a hinge layer connected to a hinge support post (210) is disclosed. The method comprises depositing a first layer of a first material to form the hinge layer (206), patterning a first mask over the first layer and selectively removing the first material not covered by any of the first mask to form a plurality of recesses, depositing a second layer of a second material over the first layer, patterning a second mask over the second layer and selectively removing the second material not covered by any of the second mask to form a hinge component (212), depositing a reflective layer (202) of a reflective material over the second layer and planarising the reflective layer (202) to form a substantially planar reflective surface.


A process for making an alignment structure in manufacturing a semiconductor device, comprising copper interconnect (Cu-interconnect) fabrication involving chemical-mechanical planarization (CMP) is disclosed. The process comprises tailoring said CMP process to produce a sufficiently high dishing on a designated alignment key area during bulk removal of Cu. The additional dishing step would have sufficient step height for optical pickup to produce alignment signal. Subsequent photolithographic processes specifically for making conventional alignment structure may thus be omitted. Preferably, the additional dishing is achieved by control over any one or combination of pressuring, vacuuming and/or venting of a CMP heads membrane, inner tube and retaining ring chambers, and selection of any one or combination of pads, slurry, pad conditioner and recipe, and may only need to achieve a removal of up to 100 {dot over (A)}. Our process may be adapted for fabricating a MIM top and MIM bottom layers via 2 masking processes, wherein the additional dishing is created as a narrow metal line. It may also be adapted for fabricating an MIM capacitor wherein the underlying Cu layer is used as the bottom plate of the MIM. The additional dishing does not appear to affect electrical properties of the underlying Cu layer.


Patent
Silterra Malaysia Sdn. Bhd. | Date: 2013-03-12

A parallel stacked symmetrical and differential inductor and manufacturing method of the same is disclosed. The parallel stacked symmetrical and differential inductor is disposed on a substrate and comprises at least one first conductive layer (202, 204) disposed on an insulating layer and at least one subsequent conductive layer (206, 208) disposed on a plurality of insulating layers stacked under the at least one first conductive layer (202, 204). The at least one first conductive layer (202, 204) and each of the at least one subsequent conductive layer (206, 208) are electrically connected by a first plurality of conductive plugs (214) in a winding region (104). Each of the at least one subsequent conductive layer (206, 208) are electrically connected by a second plurality of conductive plugs (212) in a bridge region (102).

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