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Kulim, Malaysia

Rahim S.R.A.,University of Tenaga Nasional | Ahmad I.,University of Tenaga Nasional | Chik M.A.,Silterra Malaysia Sdn. Bhd
2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings | Year: 2012

Cycle time for a product is one of the key performance indicators in semiconductor manufacturing. Reduction of cycle time will shorten product time to market, increase throughput, reduce operational cost and develop customer trust. Semiconductor manufacturing that process 40,000 to 50,000 work-in-progresses (WIP), usually takes 50 to 70 days, 300 to 400 equipments and 300 to 900 steps to complete. Thus, any task related to manual data collection to make indices reports or analysis usually needs high resources requirements to spend for manual work and risk for mistake. In the modern facility of semiconductor fabrication, a system like Manufacturing Execution Systems (MES) was implemented to ease the process and operation traceability. The information is well kept in the appropriate databases. Many applications then are integrated with MES database to perform indices reports. In this paper, the improve method for data collection related to cycle time improvement is introduced. In this approach, the automated systems was developed using existing Advance Productivity Family (APF) programming platform to collecting the data. The system is integrated between MES and APF to have the real time data collection and analysis. In the systems, manual data collection is replaced with respective automated data transfer from real situation in the manufacturing environment. This program then able to shows real root caused with proper relational charting to display real problem for engineering to prioritize and resolve respectively. As a result, 39% reduction of cycle time gained by implementing this technique. The system has successfully implemented and supports the cycle time reduction. © 2012 IEEE. Source


Abdul Wahab Y.,University of Malaya | Ahmad A.F.,Silterra Malaysia Sdn. Bhd | Hussin H.,University of Malaya | Hussin H.,University Technology of MARA | Soin N.,University of Malaya
Microelectronics Reliability | Year: 2012

Interconnects in very large scale integration (VLSI) chips are susceptible to failure due to mechanical stress in passivated interconnect lines. These mechanisms play a collective role for intensive research of thermal stability for Cu interconnects reliability in CMOS technologies. This paper presents capabilities and performance on samples annealed using furnace vs He in situ anneal and in-line technique developed to reduce total defect count. © 2012 Elsevier Ltd. All rights reserved. Source


Patent
Silterra Malaysia Sdn. Bhd. | Date: 2013-03-12

A parallel stacked symmetrical and differential inductor and manufacturing method of the same is disclosed. The parallel stacked symmetrical and differential inductor is disposed on a substrate and comprises at least one first conductive layer (


Razman H.,Silterra Malaysia Sdn. Bhd | Razman H.,University Technical Malaysia Melaka | Isa A.A.M.,University Technical Malaysia Melaka | Razali W.A.A.W.,Silterra Malaysia Sdn. Bhd | And 2 more authors.
Journal of Telecommunication, Electronic and Computer Engineering | Year: 2016

Recent studies have revealed that reticle robustness towards electrostatic field is reducing since the feature's critical dimension is getting smaller. Reticle electrostatic damage is seen after the features was subjected at low Electrostatic Discharged (ESD) voltages. This characterization was conducted on a Chrome-on-glass (COG)/Binary reticle metal layer for Complementary Metal-Oxide Semiconductor (CMOS) 250nm technology node. International Technology Roadmap for Semiconductor (ITRS) and Semiconductor Equipment and Materials International (SEMI) uses the results of this reticle electrostatic damaged characterization, extrapolates it and establishes electrostatic field limits for semiconductor industry. Generally, a semiconductor wafer fabrication company will refer to this guideline to set up an Electrostatic Protective Area (EPA) for the expansion of current facilities or new facilities. As CMOS technology node shrinks further to 130nm, the photolithography process becomes more challenging since it requires printing smaller features accurately. A newly advanced reticle, called PSM (Phase-shift Mask) reticle has been introduced. PSM reticle features are made of Molybdenum Silicide (MoSi) material, which is different from the Binary reticle that uses Chromium. Existing guideline for electrostatic control limit from ITRS and SEMI may not be sufficient to protect PSM reticle from ESD damaged due to the different material features and the smaller critical dimension (gap distance between two parallel lines). This paper proposed a future work for characterizing PSM reticle ESD threshold voltage measurement and documented the result in ITRS and SEMI as separate guideline. This study will benefit semiconductor industry to implement more accurate EPA according to reticle type and technology node. The previous characterization techniques will be reviewed and critically compared in order to gain a better understanding of the reticle ESD damaged mechanism and propose new techniques for characterizing reticle that reflect actual production environment, the latest features material and lower technology node. Source


Ibrahim K.,Silterra Malaysia Sdn. Bhd | Chik M.A.,Silterra Malaysia Sdn. Bhd | Hashim U.,University Malaysia Perlis
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2014

Semiconductor wafer manufacturing, being one of the most advanced and complex process, commands high level of utilization of the available tools to ensure maximum productivity. It is also very important to keep the operations as lean as possible to ensure cost effectiveness. In this research we will show that the cost additional capacity is outrages. This is the main reason more and more companies are opting out of fab owners club. Others are scaling down and going fables and fab-light. Capacity utilization and capacity maximization is the key to a successful fab. Fabs continuously look for ways to increase the capacity by improving productivity. Beyond certain productivity level, fabs must spend on purchasing tools. Semiconductor tools are expensive and in many cases there will be a need to spend in the support infrastructure. The escalating cost really brings out the creativity and innovation among the fab engineers. This paper discusses what actions are taken to address or mitigate this issue. The research is based on some available data from SilTerra Malaysia S dn Bhd wafer fab in Kulim. © 2014 IEEE. Source

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