Silterra Malaysia Sdn. Bhd

Kulim, Malaysia

Silterra Malaysia Sdn. Bhd

Kulim, Malaysia
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Joo T.B.,Silterra Malaysia Sdn. Bhd. | Ibrahim K.,Silterra Malaysia Sdn. Bhd. | Abd Manap N.B.,University Technical Malaysia Melaka | Salehuddin F.B.,University Technical Malaysia Melaka
Proceedings of the International Conference on Industrial Engineering and Operations Management | Year: 2016

Today's semiconductor manufacturing industry needs to improve its competitiveness by enabling new technologies and capabilities using existing equipments. Literatures show many improvements made in enabling CMOS 0.13μm technology at 0.18μm equipment platform on 200mm. This will avoid the need for additional dedicated equipments, or equipment upgrades. The fabrication process must improve to a level to increase process margin within the product specification. Almost all the capability enhancements need Capital Expenditure (CAPEX). However, enabling new technology through process improvement is the most challenging approach and usually needs very minimum capital expenditure. This paper will discuss real implementation of process improvement that successfully enabled CMOS 0.13μm technology at 0.18μm equipment platform where Shallow Trench Isolation (STI) was a constraint. The approach presented in this paper is through re-design of process development on forming new profile of STI that results in a new physical structure that is able to hold the isolation needed when current flow throughout the chip. This study utilized dataPower yield management system application, wafer position method, inline data collection and process matching. The results were successfully implemented to enable the capability for CMOS 0.13μm technology in existing factory and minimize CAPEX for 200mm semiconductor manufacturing. © IEOM Society International. © IEOM Society International.


Chik M.A.,Silterra Malaysia Sdn. Bhd | Muhamad M.R.,University Technical Malaysia Melaka
Proceedings of the International Conference on Industrial Engineering and Operations Management | Year: 2016

To meet competitive market for the electronics consumer products, the integrated circuit is process at the semiconductor fabrication factory which is the most complex and challenging areas in manufacturing. This is due to semiconductor manufacturers will require to process 300 to 1000 steps depends on products, 60,000 WIP and 400 pieces equipment for typical 200mm wafer size technology. Due to this complexity, the product mixed is highly influence the capacity of the factory. Without careful planning, a product mixed will lead to lower output and resulted to lower revenues. This is very critical due the investment cost is of a factory can reach up to USD 4 billion. Most company would like to optimize the factory as much as possible to ensure fast profit return and to ensure operational sustainability. This paper will discuss how the Industrial Engineers (IE) plays the roles for capacity management to influence the factory output based on case study of semiconductor fabrication company, SilTerra Malaysia. The methodology use for data collection and data verification is from automated systems that integrated with the equipment with real time data transaction then summarized into E10 and OEE approach. This allow more analysis for better decision to decide product mix loading plan for factory sustainability and improvement up to 14.3% of the potential revenue. © IEOM Society International. © IEOM Society International.


Mohd Darudin M.Z.,Silterra Malaysia Sdn. Bhd. | binti Khusairi N.,Silterra Malaysia Sdn. Bhd. | Ashaari H.H.,Northern University of Malaysia
Proceedings of the International Conference on Industrial Engineering and Operations Management | Year: 2016

Complementary Metal Oxide Semiconductor (CMOS) is a complex and very delicate process in semiconductor. In typical 30,000 wafer capacNity of single foundry business model, the CMOS product loads are mixed from various technologies to serve wider market segments. Total devices can be ranged from 100 to 200. This approach creates variables for process time, equipment usage, number of processing steps which leads to inconsistent WIP profiling at respective time period. A simple indication bar chart to indicate WIP quantity profile at each step is not able to indicate the overall cycle time status of WIP. Literature discussed method needed to apply for WIP planning, but limited for WIP monitoring approaches. This paper is a research regards new approach to develop WIP monitoring parameters that able to show current WIP performance, DPML performance, current WIP to allow strategy to improve WIP planning that resulted for optimize output at effective cycle time. This paper will illustrated the arithmetic for WIP parameter and real case study of approach used from the parameters in the WIP profile data to output and cycle time improvement. The benefits of this information has successfully directed to new WIP strategy that improve the quarterly output by 10% and cycle time at reasonable cycle time. © IEOM Society International. © IEOM Society International.


Bee X.E.,Silterra Malaysia Sdn. Bhd. | Fauzi M.M.B.M.,Silterra Malaysia Sdn. Bhd. | Tan P.B.Y.,Silterra Malaysia Sdn. Bhd.
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2016

In this paper, we propose a methodology to model the MOSFET subthreshold swing, S mismatch by using BSIM4 model. The 0.18μm CMOS technology silicon data show two trends in the swing mismatch plot. For large-size devices (larger than a critical area AC), the subthreshold swing behaves in a linear trend with smaller slope compared to small-size devices. A mathematical equation as a function of AC is added into the BSIM4 subthreshold swing parameter, nfactor to capture the subthreshold swing mismatch correctly. The mismatch models generated using the proposed methodology shows good agreement with the silicon data and has been tested compatible with HSPICE and SPECTRE simulators. © 2016 IEEE.


Tan C.C.,Silterra Malaysia Sdn. Bhd. | Tan P.B.Y.,Silterra Malaysia Sdn. Bhd.
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2016

In this paper, we studied the effect of mechanical stress due to Shallow Trench Isolation (STI) on the channel length direction (x-stress) and channel width direction (y-stress) by adopting two different channel orientations; <110> and <100>. When change from <110> to <100> channel orientation, PMOS sensitivity to both STI x-stress and y-stress reduces. For NMOS, both the channel orientations show the similar STI x-stress and y-stress effects. STI x-stress effects of NMOS and PMOS is contradicting. Hence, by adopting <100> channel, the performance of PMOS can be improved without degrading the NMOS performance. The STI x-stress and y-stress effects on NMOS and PMOS transistors with <110> and <100> channel orientation are explained by using the electron and hole energy valleys diagrams. © 2016 IEEE.


Tan C.C.,Silterra Malaysia Sdn. Bhd. | Tan P.B.Y.,Silterra Malaysia Sdn. Bhd.
IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE | Year: 2016

An accurate BSIM4 parameter extraction with Binning-Hybrid-Macro (BHM) methodology has been developed for MOS transistor models. The basic idea of this method is to apply binning on a hybrid-macro model. The comparison between the BHM method and various model extraction methods is discussed. BHM method is more robust and easier to use besides its capability to produce more accurate roll-off fittings compared to other methods. The BHM extraction methodology has been demonstrated on actual silicon from 0.18μm CMOS technology. Accurate model fitting to the measured data has been achieved. The model extracted using BHM method has been tested and verified to be compatible with HSPICE and SPECTRE simulators. © 2016 IEEE.


Rahim S.R.A.,University of Tenaga Nasional | Ahmad I.,University of Tenaga Nasional | Chik M.A.,Silterra Malaysia Sdn. Bhd
2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings | Year: 2012

Cycle time for a product is one of the key performance indicators in semiconductor manufacturing. Reduction of cycle time will shorten product time to market, increase throughput, reduce operational cost and develop customer trust. Semiconductor manufacturing that process 40,000 to 50,000 work-in-progresses (WIP), usually takes 50 to 70 days, 300 to 400 equipments and 300 to 900 steps to complete. Thus, any task related to manual data collection to make indices reports or analysis usually needs high resources requirements to spend for manual work and risk for mistake. In the modern facility of semiconductor fabrication, a system like Manufacturing Execution Systems (MES) was implemented to ease the process and operation traceability. The information is well kept in the appropriate databases. Many applications then are integrated with MES database to perform indices reports. In this paper, the improve method for data collection related to cycle time improvement is introduced. In this approach, the automated systems was developed using existing Advance Productivity Family (APF) programming platform to collecting the data. The system is integrated between MES and APF to have the real time data collection and analysis. In the systems, manual data collection is replaced with respective automated data transfer from real situation in the manufacturing environment. This program then able to shows real root caused with proper relational charting to display real problem for engineering to prioritize and resolve respectively. As a result, 39% reduction of cycle time gained by implementing this technique. The system has successfully implemented and supports the cycle time reduction. © 2012 IEEE.


Patent
Silterra Malaysia Sdn. Bhd. | Date: 2012-12-28

A method for manufacturing a planarised reflective layer disposed on a hinge layer connected to a hinge support post (210) is disclosed. The method comprises depositing a first layer of a first material to form the hinge layer (206), patterning a first mask over the first layer and selectively removing the first material not covered by any of the first mask to form a plurality of recesses, depositing a second layer of a second material over the first layer, patterning a second mask over the second layer and selectively removing the second material not covered by any of the second mask to form a hinge component (212), depositing a reflective layer (202) of a reflective material over the second layer and planarising the reflective layer (202) to form a substantially planar reflective surface.


A process for making an alignment structure in manufacturing a semiconductor device, comprising copper interconnect (Cu-interconnect) fabrication involving chemical-mechanical planarization (CMP) is disclosed. The process comprises tailoring said CMP process to produce a sufficiently high dishing on a designated alignment key area during bulk removal of Cu. The additional dishing step would have sufficient step height for optical pickup to produce alignment signal. Subsequent photolithographic processes specifically for making conventional alignment structure may thus be omitted. Preferably, the additional dishing is achieved by control over any one or combination of pressuring, vacuuming and/or venting of a CMP heads membrane, inner tube and retaining ring chambers, and selection of any one or combination of pads, slurry, pad conditioner and recipe, and may only need to achieve a removal of up to 100 {dot over (A)}. Our process may be adapted for fabricating a MIM top and MIM bottom layers via 2 masking processes, wherein the additional dishing is created as a narrow metal line. It may also be adapted for fabricating an MIM capacitor wherein the underlying Cu layer is used as the bottom plate of the MIM. The additional dishing does not appear to affect electrical properties of the underlying Cu layer.


Patent
Silterra Malaysia Sdn. Bhd. | Date: 2013-03-12

A parallel stacked symmetrical and differential inductor and manufacturing method of the same is disclosed. The parallel stacked symmetrical and differential inductor is disposed on a substrate and comprises at least one first conductive layer (202, 204) disposed on an insulating layer and at least one subsequent conductive layer (206, 208) disposed on a plurality of insulating layers stacked under the at least one first conductive layer (202, 204). The at least one first conductive layer (202, 204) and each of the at least one subsequent conductive layer (206, 208) are electrically connected by a first plurality of conductive plugs (214) in a winding region (104). Each of the at least one subsequent conductive layer (206, 208) are electrically connected by a second plurality of conductive plugs (212) in a bridge region (102).

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