Sunnyvale, CA, United States

Silicon Storage Technology

www.sst.com
Sunnyvale, CA, United States

Microchip Technology is an American manufacturer of microcontroller, memory and analog semiconductors. Its products include microcontrollers , Serial EEPROM devices, Serial SRAM devices, KEELOQ devices, radio frequency devices, thermal, power and battery management analog devices, as well as linear, interface and mixed signal devices.Some of the interface devices include USB, ZigBeetest facilities in Chachoengsao, Thailand. Sales for the fiscal year ending on March 31, 2014 were $1,931,217,000.Among its chief competitors are Analog Devices, Atmel, Freescale , Infineon, Maxim Integrated Products, NXP Semiconductors , Renesas Electronics, STMicroelectronics, and Texas Instruments. Wikipedia.

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Patent
Silicon Storage Technology | Date: 2017-05-31

A bitline regulator for use in a high speed flash memory system is disclosed. The bitline regulator is responsive to a set of trim bits that are generated by comparing the bias voltage of a bitline to a reference voltage.


Patent
Silicon Storage Technology | Date: 2017-01-11

Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.


Patent
Silicon Storage Technology | Date: 2017-04-05

A system and method for improved power sequencing within an embedded flash memory device is disclosed.


Patent
Silicon Storage Technology | Date: 2017-05-10

Disclosed is a system comprising a phase error detector (130) for determining the phase error between a first periodic signal (CLKS) and a second periodic signal (CLKFB); a counter (140) for receiving one or more outputs from the phase error detector (130) and generating a digital signal (FT CT); and a controller (150) for receiving the digital signal and generating a signal to drive a current control delay loop (160), the current control delay loop (160) generating the second periodic signal (CLKFB) and the timing delay signal (DLY).


A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited.


An improved control gate decoding design for reducing disturbances during the programming of flash memory cells is disclosed. In one embodiment, a control gate line decoder is coupled to a first control gate line associated with a row of flash memory cells in a first sector and to a second control gate line associated with a row of flash memory cells in a second sector.


Patent
Silicon Storage Technology | Date: 2017-03-08

A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.


Patent
Silicon Storage Technology | Date: 2017-06-14

The present invention relates to a flash memory device with EEPROM functionality. The flash memory device is byte-erasable and bit-programmable.


A non- volatile memory cell includes a semiconductor substrate of first conductivity type, first and second spaced-apart regions in the substrate of second conductivity type, with a channel region in the substrate there between. A floating gate has a first portion disposed vertically over a first portion of the channel region, and a second portion disposed vertically over the first region. The floating gate includes a sloping upper surface that terminates with one or more sharp edges. An erase gate is disposed vertically over the floating gate with the one or more sharp edges facing the erase gate. A control gate has a first portion disposed laterally adjacent to the floating gate, and vertically over the first region. A select gate has a first portion disposed vertically over a second portion of the channel region, and laterally adjacent to the floating gate.


Patent
Silicon Storage Technology | Date: 2017-01-25

A semiconductor device has a silicon substrate with a first area (20) including a buried insulation layer (10b) with silicon over and under the insulation layer and a second area (22) in which the substrate lacks buried insulation disposed under any silicon. Logic MOS devices (62) are formed in the first area in the silicon (10c) that is over the insulation layer. Memory cells (49) are formed in the second area that include spaced apart second source and second drain regions (42, 48) formed in the substrate and defining a channel region (47) therebetween, a floating gate (34) disposed over and insulated from a first portion of the channel region, and a select gate (44) disposed over and insulated from a second portion of the channel region.

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