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Hsinchu, Taiwan

Yeh K.-L.,National Chiao Tung University | Yeh K.-L.,Silicon Motion Technology | Guo J.-C.,National Chiao Tung University
IEEE Transactions on Electron Devices | Year: 2013

The impact of narrow-width effects on high-frequency performance like fT, fMAX, and RF noise parameters, such as NF min and Rn, in sub-40-nm multifinger CMOS devices is investigated in this paper. Narrow-oxide-diffusion (OD) MOSFET with smaller finger width and larger finger number can achieve lower Rg and higher fMAX. However, these narrow-OD devices suffer fT degradation and higher NFmin, even with the advantage of lower R g. The mechanisms responsible for the tradeoff between different parameters will be presented to provide an important guideline of multifinger MOSFET layout for RF circuit design using nanoscale CMOS technology. © 1963-2012 IEEE.

Lin C.-H.,Yuan Ze University | Chen C.-Y.,Silicon Motion Technology | Chang E.-J.,National Taiwan University | Wu A.-Y.,National Taiwan University
2011 International Symposium on Integrated Circuits, ISIC 2011 | Year: 2011

This paper presents a turbo decoder chip design supporting distinct convolutional turbo code schemes in WiMAX and LTE systems. A contention-free vectorizable dual-standard interleaver is proposed to enhance the hardware utilization. Moreover, a warm-up free parallel MAP decoding is proposed to improve the throughput rate. The overall VLSI architecture of the proposed CTC decoder is presented for supporting the WiMAX/LTE systems. This chip fabricated in a core area of 3.38 mm 2 by 90nm CMOS process is measured at 152 MHz with a power consumption of 148.1 mW and a throughput rate of 186.1 Mbps. This chip achieves a high area efficiency of 0.36 bit/mm 2 and a low energy efficiency 0.16 nJ/bit/iteration. © 2011 IEEE.

Lin C.-H.,Yuan Ze University | Chen C.-Y.,Silicon Motion Technology | Chang E.-J.,National Taiwan University | Wu A.-Y.,National Taiwan University
Journal of Signal Processing Systems | Year: 2013

For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multi-standard turbo decoder chip is fabricated in a core area of 3.38 mm2 by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard. © 2013 Springer Science+Business Media New York.

Ueng Y.-L.,National Tsing Hua University | Wang Y.-L.,MediaTek Inc. | Kan L.-S.,Silicon Motion Technology | Yang C.-J.,National Tsing Hua University | Su Y.-H.,National Tsing Hua University
IEEE Transactions on Signal Processing | Year: 2012

In this paper, we jointly design architecture-aware (AA) low-density parity-check convolutional codes (LDPC-CCs) and the associated memory-based decoder architecture based on shuffled message-passing decoding (MPD). We propose a method for constructing AA-LDPC-CCs that can facilitate the design of a memory-based shuffled decoder using parallelization in both iteration and node dimensions. Through the use of shuffled MPD, the number of base processors and, hence, the decoder area is significantly reduced, since a fewer number of iterations is required in order to achieve a desired error performance. In addition, the use of memory instead of registers minimizes the implementation cost of each base processor. In the memory-based decoder, collisions in memory access can be avoided and the difficulty in exchanging information between iterations (processors) is overcome by using simple permutation networks. To demonstrate the feasibility of the proposed techniques, we constructed a time-varying (479, 3, 6) AA-LDPC-CC and implemented its associated shuffled decoder using a 90-nm CMOS process. This decoder comprises 11 processors, occupies an area of 5.36 mm 2, and achieves an information throughput of 1.025 Gbps at a clock frequency of 256.4 MHz based on post-layout results. © 2012 IEEE.

News Article | December 23, 2011
Site: bgr.com

News broke earlier this week that Apple has acquired Israel-based fabless flash memory firm Anobit for as much as $400 million according to TheMarker, adding another leading chip maker to the company’s portfolio. Anobit’s NAND flash memory is already used in Apple products including the iPhone and iPad, and the firm’s technology is said to offer several advantages over that of its rivals. As DigiTimes pointed out in a recent report, the move also means Anobit’s other clients are now forced to look elsewhere as Apple becomes the exclusive owner of Anobit’s chip technology. Major players including Hynix and Micron were Anobit partners in the past, taking advantage of the company’s proprietary technology that improves the performance and lifespan of its flash memory products. Hynix, Micron and others are now reportedly looking to Taiwan-based companies including Phison Electronics and Silicon Motion Technology following the acquisition. Direct gains from Apple’s Anobit buy include the company’s technology and talent, but another advantage over rivals now emerges as a clear secondary benefit — smartphone vendors that used NAND flash memory chips made by soon-to-be former Anobit clients will no longer be able to utilize Anobit’s class-leading technology.

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