Huntsville, AL, United States
Huntsville, AL, United States

Silicon Laboratories, Inc. is a mixed signal fabless semiconductor company based in Austin, Texas.The company was founded in 1996 by three veterans from the former Crystal Semiconductor – Nav Sooch, Dave Welland and Jeff Scott. The company's CEO is Tyson Tuttle. The company went public in 2000. Silicon Labs leverages its intellectual property to develop mixed-signal ICs that typically integrate a number of discrete functions on a single CMOS die. The company has leveraged its technology portfolio to expand into a number of large markets. The company has three main businesses: Access - which includes analog modems for set-top boxes, point of sale terminals and multi-function printers, SLICs for VoIP gateways, and PoE devices for networking Broadcast - which includes single-chip AM/FM radios and silicon TV tuners and demodulators Broad-based - which includes 8-bit and 32-bit microcontrollers, low power wireless ICs and sensors targeted at the Internet of Things, and timing clocks, oscillators buffers and digital isolators targeted at internet infrastructure.Silicon Labs has about 1,050 employees worldwide and research and development offices located throughout the US, Europe, and Asia. Wikipedia.


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Patent
Silicon Laboratories | Date: 2015-11-05

A technique includes switching a supply rail from receiving a first voltage to receiving a second voltage; and regulating a slew rate associated with the switching.


Patent
Silicon Laboratories | Date: 2016-12-23

Various techniques for reducing power in a wireless network device are disclosed. In some embodiments, software routines within the device are modified to minimize the time during which the analog circuitry in a radio is powered. In some embodiments, the techniques make use of knowledge of implied delays associated with a particular network protocol. For example, in a CSMA network, there is a defined minimum period before the device can attempt to gain access to the media. The radio may be powered off during this defined period. In other embodiments, modifications to a protocol are disclosed which allow additional power savings.


An apparatus includes a first integrated circuit (IC) that includes a first radio-frequency (RF) circuit to process RF signals, a first antenna port to couple to one or more antennas, and a first switch integrated in the first IC and coupled to the first antenna port. The apparatus further includes a second IC that includes a second RF circuit to process RF signals, a second antenna port to couple to the one or more antennas, and a second switch integrated in the second IC and coupled to the second antenna port.


Patent
Silicon Laboratories | Date: 2015-10-30

Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.


An apparatus includes a first electromagnetic sensor configured to generate a first sensed signal based at least in part on detection of a first signal having a first wavelength. The apparatus includes a second electromagnetic sensor configured to generate a second sensed signal based at least in part on detection of a second signal having a second wavelength different from the first wavelength. The apparatus includes a processing circuit configured to generate a plethysmogram based at least in part on the first sensed signal and the second sensed signal. The apparatus may include a first emitter configured to emit an optical signal having the first wavelength. The apparatus may include a second emitter configured to emit a reference signal. The first wavelength may be a human-blood-sensitive and human-skin-penetrable wavelength and the second wavelength may be at least one of a human-blood-insensitive wavelength and a human-skin-impenetrable wavelength.


Patent
Silicon Laboratories | Date: 2015-10-30

A capacitor sense system includes a pad for coupling to an external capacitor. A current digital to analog converter (DAC) supplies current to charge the external capacitor. A reference capacitor is charged by a current source. A first comparator compares a voltage across the external capacitor sensed at the pad to a reference voltage and generates a first comparison. A second comparator compares a voltage across a reference capacitor to the reference voltage and generates a second comparison. The stored first and second comparisons are used to control the current DAC. First and second AC coupling capacitors are coupled respectively between the pad and the first comparator and between the reference capacitor and the second comparator. Sensing at the pad allows more accuracy and the AC coupling capacitors provide better matching and allow for different DC biases to be set for the external capacitor and the first comparator.


Patent
Silicon Laboratories | Date: 2015-10-21

A low-noise voltage reference generator that utilizes internal gain and feedback to generate an output signal having reduced sensitivity to power supply variations and loading conditions is described. A method includes generating a current based on a voltage drop across a resistor. The voltage drop is based on a second voltage drop across a gate terminal of a transistor and a source terminal of the transistor. The method includes the current using a reference voltage to generate a mirrored current through a node coupled to the drain terminal of the transistor. The method includes generating a level-shifted voltage using a voltage on the node. The method includes buffering the level-shifted voltage using a power supply voltage to generate the reference voltage.


Patent
Silicon Laboratories | Date: 2015-11-17

A computing system includes a central processing unit (CPU) connected to communicate over a bus, a memory configured to have at least three accessible memory storage areas arranged asymmetrically and a memory protection unit (MPU) that receives and controls memory access requests received from the central processing unit and from other processing devices, blocks or processes. The MPU determines, based on an identity of the device, block or process that generated the memory access request, whether to allow access based upon which memory area is being accessed and a type of access being requested. The areas of memory include read/write for secure and non-secure, read/write for secure only, and read for secure and non-secure but write only for secure.


Patent
Silicon Laboratories | Date: 2016-06-21

In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.


An apparatus includes a radio frequency (RF) receiver having a multi-bit observation interval. The RF receiver includes a Coordinate Rotation Digital Computer (Cordic) circuit to receive a complex signal derived from RF signals and to generate a phase signal. The RF receiver further includes a timing correlator and frequency offset estimator coupled to receive data derived from a frequency signal derived from the phase signal. The RF receiver in addition includes a Viterbi decoder coupled to provide decoded data derived from the frequency signal.

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