Huntsville, AL, United States

Silicon Laboratories

silabs.com
Huntsville, AL, United States

Silicon Laboratories, Inc. is a mixed signal fabless semiconductor company based in Austin, Texas.The company was founded in 1996 by three veterans from the former Crystal Semiconductor – Nav Sooch, Dave Welland and Jeff Scott. The company's CEO is Tyson Tuttle. The company went public in 2000. Silicon Labs leverages its intellectual property to develop mixed-signal ICs that typically integrate a number of discrete functions on a single CMOS die. The company has leveraged its technology portfolio to expand into a number of large markets. The company has three main businesses: Access - which includes analog modems for set-top boxes, point of sale terminals and multi-function printers, SLICs for VoIP gateways, and PoE devices for networking Broadcast - which includes single-chip AM/FM radios and silicon TV tuners and demodulators Broad-based - which includes 8-bit and 32-bit microcontrollers, low power wireless ICs and sensors targeted at the Internet of Things, and timing clocks, oscillators buffers and digital isolators targeted at internet infrastructure.Silicon Labs has about 1,050 employees worldwide and research and development offices located throughout the US, Europe, and Asia. Wikipedia.

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Patent
Silicon Laboratories | Date: 2015-11-17

A computing system includes a central processing unit (CPU) connected to communicate over a bus, a memory configured to have at least three accessible memory storage areas arranged asymmetrically and a memory protection unit (MPU) that receives and controls memory access requests received from the central processing unit and from other processing devices, blocks or processes. The MPU determines, based on an identity of the device, block or process that generated the memory access request, whether to allow access based upon which memory area is being accessed and a type of access being requested. The areas of memory include read/write for secure and non-secure, read/write for secure only, and read for secure and non-secure but write only for secure.


Patent
Silicon Laboratories | Date: 2016-01-28

A processor, such as a low-cost microcontroller unit, uses a DMA controller to facilitate direct memory transactions between hardware subsystems independently of the CPU. To enable those transactions to be carried out security, gateways are provided to the DMA controller and peripheral bridge. The gateways, which have access to multiple access policies, switch between those policies depending on a hardware context and/or subcontext, such as the bus master originating the transaction and/or the DMA channel associated with the transaction. The gateways are operable to administer those policies independently of the CPU. In various implementations, gateways are provided for the DMA controller, the peripheral bridge, and/or individual peripherals. The processor is able to support secure, fully containerized operations involving its peripherals without constant CPU intervention.


Patent
Silicon Laboratories | Date: 2017-03-28

In one form, an oscillator includes an oscillator core circuit and a dynamic gain control circuit. The oscillator core circuit is for connection to a frequency reference element and provides a first clock signal using a negative gain element having a gain determined by a gain control signal. The dynamic gain control circuit is coupled to the oscillator core circuit for calibrating the gain control signal to a startup value based on oscillations reaching a first threshold during a startup state, and calibrating the gain control signal to a steady-state value based on oscillations falling to a second threshold after an end of the startup state and before entering a steady state. The first threshold is higher than the second threshold. The dynamic gain control circuit operates the oscillator core circuit during the steady state using the steady-state value.


A signal processor for a radio frequency (RF) receiver includes a signal processing path having first and second programmable gain amplifiers and first and second offset correction circuits. The first offset correction circuit receives a first digital offset correction word and corrects a first offset of the first programmable gain amplifier by adding a first value corresponding to the first digital offset correction word to an input of the first programmable gain amplifier. The second offset correction circuit receives a second digital offset correction word and corrects a second offset of the second programmable gain amplifier by adding a first value corresponding to the second digital offset correction word to an input of the second programmable gain amplifier. A controller measures offsets of the first and second programmable gain amplifiers during a calibration, and provides the first and second offset correction words in response to the offsets.


Patent
Silicon Laboratories | Date: 2016-11-22

Current flowing through an inductor on a primary side of a voltage converter is sensed and compared to a threshold peak current value to determine when to end an ON portion of the voltage converter. The secondary side of the voltage converter supplies an indication of output voltage for use in determining the threshold peak current value. On start-up the primary side detects when the indication of output voltage is supplied by the secondary side across on isolation channel. Prior to detecting the indicating is being supplied, the primary side uses an increasing threshold peak current as the threshold peak current value. After detection that the indication of output voltage is being provided by the secondary side, the threshold peak current value is based on the indication of the output voltage.


Patent
Silicon Laboratories | Date: 2016-12-23

Various techniques for reducing power in a wireless network device are disclosed. In some embodiments, software routines within the device are modified to minimize the time during which the analog circuitry in a radio is powered. In some embodiments, the techniques make use of knowledge of implied delays associated with a particular network protocol. For example, in a CSMA network, there is a defined minimum period before the device can attempt to gain access to the media. The radio may be powered off during this defined period. In other embodiments, modifications to a protocol are disclosed which allow additional power savings.


An apparatus includes a first integrated circuit (IC) that includes a first radio-frequency (RF) circuit to process RF signals, a first antenna port to couple to one or more antennas, and a first switch integrated in the first IC and coupled to the first antenna port. The apparatus further includes a second IC that includes a second RF circuit to process RF signals, a second antenna port to couple to the one or more antennas, and a second switch integrated in the second IC and coupled to the second antenna port.


Patent
Silicon Laboratories | Date: 2016-06-21

In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value.


An apparatus includes a radio frequency (RF) receiver having a multi-bit observation interval. The RF receiver includes a Coordinate Rotation Digital Computer (Cordic) circuit to receive a complex signal derived from RF signals and to generate a phase signal. The RF receiver further includes a timing correlator and frequency offset estimator coupled to receive data derived from a frequency signal derived from the phase signal. The RF receiver in addition includes a Viterbi decoder coupled to provide decoded data derived from the frequency signal.


Patent
Silicon Laboratories | Date: 2016-04-12

An integrated clock generator includes a tunable LC oscillator, a tunable frequency synthesizer, and a processor. The tunable LC oscillator has an input for receiving an oscillator control signal, and an output for providing an oscillator clock signal. The tunable frequency synthesizer has a clock input coupled to the output of the tunable LC oscillator, a control input for receiving a synthesizer control signal, and an output for providing a clock output signal. The processor has an input for receiving a data input signal, a first output for providing the oscillator control signal, and a second output for providing the synthesizer control signal. The processor provides the oscillator control signal and the synthesizer control signal such that the tunable frequency synthesizer generates the output clock signal at a frequency indicated by the data input signal, and provides the synthesizer control signal further in response to a dynamic condition.

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