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Stoneham, MA, United States

Moorby P.,Sigmatix | Lin Y.,Sigmatix | Mlinarsky F.,Octo Scope
Electronic Engineering Times | Year: 2010

Software-defined radio (SDR) promises to replace the growing number of specialized radio chips on the handset circuit board with a single, multimode-programmable device. SDR reduces the number of radio devices in a handset by up to five times, thereby cutting costs, simplifying design and increasing battery life. It provides wider coverage by reprogramming itself to operate on diverse international networks. It improves customer satisfaction and reduces development risk by enabling over-the-air bug fixes and upgrades as standards evolve. With the rise of vector computing architectures, software radio performance can compete with that of custom hardware. Vector processors are particularly well suited to supporting baseband implementations. Multimode vector radio represents the next generation of SDR, enabling the flexibility of the software approach with the performance levels of a hardware implementation. Software synthesis allows portability and hardware-level optimization for MVR not previously possible with standard compilers. Source

Keif D.,Sigmatix | Moorby P.,Sigmatix
Electronic Engineering Times | Year: 2010

The wireless companies are converging to drive practical software-defined radio (SDR) implementations. Vector processing architectures are being put forward that are targeted at wireless baseband usage, with specialized instruction sets, streamlined storage access mechanisms and, most important, multiple forms of parallelism. The barrier to SDR is the programmability of vector processors. Leveraging multiple levels of parallelism and making every part of the parallel architecture and storage access count on every clock cycle is a highly complex software engineering problem that does not lend itself to automation. Single-instruction, multiple-data (SIMD) data paths enable a flexible number of parallel lanes. Combining this with very long instruction word (VLIW) pipelines, wherein multiple operations may be executed on every clock cycle, engineers have a processing matrix that can be packed onto silicon more efficiently than by multiplying processor cores. Source

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