Sichuan Institute of Solid State Circuits

Chongqing, China

Sichuan Institute of Solid State Circuits

Chongqing, China

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Guo A.,Sichuan Institute of Solid State Circuits | Hu R.B.,Science and Technology on Analog Integrated Circuit Laboratory
Applied Mechanics and Materials | Year: 2014

A capacitor memory erasing technique for pipeline ADC is introduced, which insert a clearing phase to the traditional working timing sequence of the MDAC to erasing the residual charges on the sampling capacitor. The measurement shows that the 14-bit pipeline ADC adopting the proposed technique can achieve a sampling rate of 250MSPS with SNR 69dB, SFDR 80dB, compared with the traditional ADC of sampling rate 100MSPS, SNR 60dB, SFDR 71dB, which proves the proposed technique can improve the performances of pipeline ADCS obviously. © (2014) Trans Tech Publications, Switzerland.


Xu X.,Sichuan Institute of Solid State Circuits | Jiang J.,Sichuan Institute of Solid State Circuits
Mechatronics Engineering and Electrical Engineering - Proceedings of the 2014 International Conference on Mechatronics Engineering and Electrical Engineering, CMEEE 2014 | Year: 2015

The development direction of bandgap voltage in low temperature drift, heavy load and can be adjusted. This paper presents a novel single-stage reference source; this source has adjustable output voltage, and reduces the effect of the offset voltageand overcome the non-adjustable of former references. This reference source can carry heavy load, has the same compensation coefficient with regular structure and has good Power Supply Rejection Ratio (PSRR). © 2015 Taylor & Francis Group, London.


Ye R.,Sichuan Institute of Solid State Circuits | Hu R.,Science and Technology on Analog Integrated Circuit Laboratory
2013 International Conference on Optoelectronics and Microelectronics, ICOM 2013 | Year: 2013

A novel pre-amplifying and latching comparator is presented, which has several advantages over the traditional one. At first, its preamplifier has three stages, which provides larger gain and wider bandwidth at the same time. Secondly, the outputs of the latch are directly driven by the preamplifier, which will reduce the latching time. Additionally, a pair of capacitors is inserted between the latch and the preamplifier, which reduces the offset of the preamplifier further. The simulated results show that the proposed comparator has an analog bandwidth of 5GHz with sampling rate of 2GHz, which is better than the traditional one. © 2013 IEEE.


Hu R.,Science and Technology on Analog Integrated Circuit Laboratory | Ye R.,Sichuan Institute of Solid State Circuits
2013 International Conference on Optoelectronics and Microelectronics, ICOM 2013 | Year: 2013

A kind of 3-bit flash ADC core is presented, which adopts CMOS inverter as comparators and PLA encoding scheme, and is very suitable for standard digital CMOS process and easy to be integrated with digital circuits, such as CPU, memory, etc. The optimization of the 3-bit ADC core is given and the simulation shows that the proposed ADC core can achieve 2Gsps sampling rate while consuming only 0.56mW power. © 2013 IEEE.


Hu R.,Science and Technology on Analog Integrated Circuit Laboratory | Zhang X.,Sichuan Institute of Solid State Circuits
2015 International Conference on Optoelectronics and Microelectronics, ICOM 2015 | Year: 2015

A switch-decoded based current-steering architecture is proposed for calibration DAC of ADCs. The circuit and working principle of the proposed switch-decoded current-steering DAC is introduced. A 14-bit DAC is realized in 0.18um CMOS process by combining an 8-bit switch-decoded current-steering DAC with a 6-bit binary-weight DAC. The chip area taken by the 14-bit DAC is only 0.1 square millimeters. The simulation shows that the DNL is +0.18/-0.52LSB and the INL is +1.5/-2.3LSB. © 2015 IEEE.


Hu R.,Science and Technology on Analog Integrated Circuit Laboratory | Zhang X.,Sichuan Institute of Solid State Circuits
2015 International Conference on Optoelectronics and Microelectronics, ICOM 2015 | Year: 2015

A CMOS analog front end for ADCs is introduced, which can sample and hold the incoming analog signal for the following ADC. As a result, the ADC can deal with a signal which is unchanged at the working period of the ADC. The analog front is a full differential architecture including two completely symmetrical signal paths, which receive the normal and inverted phase parts of a full differential signal, respectively. The outputs of the two signal paths are inputted into the normal and inverted phase input terminals of a full differential amplifier. A protection is added to the circuit to speed up the sampling switch. A resistor is added to filter out the high frequency spur caused by the switching action of circuit. As a result, the proposed circuit has higher sampling rate and performances than other related sample and hold circuit. Simulation shows that the analog front consumes only 80mW power and has a SNR of 67dB as well as a SFDR of 70dB at a sampling rate of 2.4GSPS. © 2015 IEEE.


Ye R.K.,Sichuan Institute of Solid State Circuits | Hu R.B.,Science and Technology on Analog Integrated Circuit Laboratory
Advanced Materials Research | Year: 2014

A kind of CMOS bandgap reference circuit with high order temperature compensation is introduced [1]. Compared to the traditional circuit, the bandgap reference proposed here has several advantages such as better temperature stability, smaller chip area, lower power consumption, self power-on, and so on. Our design can be used in analog-to-digital or digital-to-analog converters, where high performance bandgap reference is required. © (2014) Trans Tech Publications, Switzerland.


Hu R.,Sichuan Institute of Solid State Circuits | Tang J.,Chongqing University of Posts and Telecommunications | Tang J.,Science and Technology on Analog Integrated Circuit Laboratory
2012 2nd International Conference on Consumer Electronics, Communications and Networks, CECNet 2012 - Proceedings | Year: 2012

A novel bootstrapped switch is introduced in this paper At first, the mathematics built in the bootstrapped switch is discussed Secondly, the prototype of the bootstrapped switch is described. At last, the transistor-level circuit of the bootstrapped switch is given. The performance of the bootstrapped switch is tested indirectly by stimulating a sampling and holding circuit containing the bootstrapped switch. The stimulated results show that the bootstrapped switch has a performance with SFDR more than 89dBc, and SNR bigger than 79dB. © 2012 IEEE.


Hu R.,Sichuan Institute of Solid State Circuits | Tang J.,Chongqing University of Posts and Telecommunications | Tang J.,Science and Technology on Analog Integrated Circuit Laboratory
2012 2nd International Conference on Consumer Electronics, Communications and Networks, CECNet 2012 - Proceedings | Year: 2012

A novel full differential double sampling circuit is presented in the paper. The traditional full differential single sampling circuit is compared with the proposed full differential double sampling one to show that the latter has more efficiency and higher speed The proposed full differential double sampling circuit is designed in TSMC 0.18m CMOS process technology. The simulation results show that the SFDR of the proposed full differential double sampling circuit is 81.36dB at 200MS/s. Further simulations show that the proposed full differential double sampling circuit has twice better performance than the traditional one. © 2012 IEEE.


Jing Z.,Chongqing Optoelectronics Research Institute | Pu L.,Sichuan Institute of Solid state Circuits
2014 31th URSI General Assembly and Scientific Symposium, URSI GASS 2014 | Year: 2014

This paper presents a novel charge pump which overcomes the limitation of low image signal swing and long reset time in the four transistor CMOS active pixel image sensor. Unlike the conventional charge pumps in the literature, the output of the voltage doubler does not directly connected to the load. Alternatively, the high voltage is served as the power supply to a reference buffer. A high precision reference voltage is fed to the reference buffer. Thus, low voltage ripple is achieved with this architecture. In order to control the output voltage within the required range, a feedback loop is included. The simulation results show that with this architecture, the output of the charge pump is enhanced from 1.05V to 4.1V with ripple less than 2mV when driving a 764×524 CMOS image sensor. © 2014 IEEE.

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