Entity

Time filter

Source Type


Guo A.,Sichuan Institute of Solid State Circuits | Hu R.B.,Science and Technology on Analog Integrated Circuit Laboratory
Applied Mechanics and Materials | Year: 2014

A capacitor memory erasing technique for pipeline ADC is introduced, which insert a clearing phase to the traditional working timing sequence of the MDAC to erasing the residual charges on the sampling capacitor. The measurement shows that the 14-bit pipeline ADC adopting the proposed technique can achieve a sampling rate of 250MSPS with SNR 69dB, SFDR 80dB, compared with the traditional ADC of sampling rate 100MSPS, SNR 60dB, SFDR 71dB, which proves the proposed technique can improve the performances of pipeline ADCS obviously. © (2014) Trans Tech Publications, Switzerland. Source


Ye R.,Sichuan Institute of Solid State Circuits | Hu R.,Science and Technology on Analog Integrated Circuit Laboratory
2013 International Conference on Optoelectronics and Microelectronics, ICOM 2013 | Year: 2013

A novel pre-amplifying and latching comparator is presented, which has several advantages over the traditional one. At first, its preamplifier has three stages, which provides larger gain and wider bandwidth at the same time. Secondly, the outputs of the latch are directly driven by the preamplifier, which will reduce the latching time. Additionally, a pair of capacitors is inserted between the latch and the preamplifier, which reduces the offset of the preamplifier further. The simulated results show that the proposed comparator has an analog bandwidth of 5GHz with sampling rate of 2GHz, which is better than the traditional one. © 2013 IEEE. Source


Hu R.,Science and Technology on Analog Integrated Circuit Laboratory | Ye R.,Sichuan Institute of Solid State Circuits
2013 International Conference on Optoelectronics and Microelectronics, ICOM 2013 | Year: 2013

A kind of 3-bit flash ADC core is presented, which adopts CMOS inverter as comparators and PLA encoding scheme, and is very suitable for standard digital CMOS process and easy to be integrated with digital circuits, such as CPU, memory, etc. The optimization of the 3-bit ADC core is given and the simulation shows that the proposed ADC core can achieve 2Gsps sampling rate while consuming only 0.56mW power. © 2013 IEEE. Source


Hu R.,Science and Technology on Analog Integrated Circuit Laboratory | Zhang X.,Sichuan Institute of Solid State Circuits
2015 International Conference on Optoelectronics and Microelectronics, ICOM 2015 | Year: 2015

A switch-decoded based current-steering architecture is proposed for calibration DAC of ADCs. The circuit and working principle of the proposed switch-decoded current-steering DAC is introduced. A 14-bit DAC is realized in 0.18um CMOS process by combining an 8-bit switch-decoded current-steering DAC with a 6-bit binary-weight DAC. The chip area taken by the 14-bit DAC is only 0.1 square millimeters. The simulation shows that the DNL is +0.18/-0.52LSB and the INL is +1.5/-2.3LSB. © 2015 IEEE. Source


Hu R.,Science and Technology on Analog Integrated Circuit Laboratory | Zhang X.,Sichuan Institute of Solid State Circuits
2015 International Conference on Optoelectronics and Microelectronics, ICOM 2015 | Year: 2015

A CMOS analog front end for ADCs is introduced, which can sample and hold the incoming analog signal for the following ADC. As a result, the ADC can deal with a signal which is unchanged at the working period of the ADC. The analog front is a full differential architecture including two completely symmetrical signal paths, which receive the normal and inverted phase parts of a full differential signal, respectively. The outputs of the two signal paths are inputted into the normal and inverted phase input terminals of a full differential amplifier. A protection is added to the circuit to speed up the sampling switch. A resistor is added to filter out the high frequency spur caused by the switching action of circuit. As a result, the proposed circuit has higher sampling rate and performances than other related sample and hold circuit. Simulation shows that the analog front consumes only 80mW power and has a SNR of 67dB as well as a SFDR of 70dB at a sampling rate of 2.4GSPS. © 2015 IEEE. Source

Discover hidden collaborations