Shennan, China
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Ding P.,Shennan Circuits Co. | Liu R.,Shennan Circuits Co. | Chen Y.,Tsinghua University | Song G.,Shennan Circuits Co. | Li G.,Shennan Circuits Co.
Proceedings of the Electronic Packaging Technology Conference, EPTC | Year: 2014

Interface delamination is one major reliability problem that may lead to multi-material structures products failure in microsystems package. To ensure the package reliability and to provide guidelines for package design and manufacture, a series of experiments are designed to study the adhesive strength between substrate and molding compound(MC) through charging molding parameters. On the other hand, the adhesive strength, disposed by Moisture sensitivity level 3(MSL3) and reflowed three times at 260 centigrade, is investigated. Finally, some details related with package design and manufacture are given out for reference. © 2014 IEEE.

Gu X.,Shennan Circuits Co. | Gu X.,City University of Hong Kong | Yung K.C.,Hong Kong Polytechnic University | Chan Y.C.,City University of Hong Kong | Yang D.,City University of Hong Kong
Journal of Materials Science: Materials in Electronics | Year: 2011

Individual effect of thermomigration (TM) and combined effect of TM and electromigration (EM) on the microstructural variation in Sn8Zn3Bi was investigated by stressing line-type Au/Ni-P/Cu-Sn8Zn3Bi-Au/Ni-P/Ni solder joints with a 5 × 10 3A/cm 2 alternating current (AC) or direct current (DC) at 110°C. Due to the different thermoelectric characteristics of Cu and Ni wires, a thermal gradient of 196°C/cm could be established across the solder joints according to the finite element simulation. In AC current stressing, there is no EM effect and only TM dominates the migration. Microstructural study shows that Zn atoms migrate towards the lower temperature side during TM. In DC current stressing, it is found that both EM and TM play important roles depending various experimental conditions. And the energy change during the EM and the TM is estimated to be δω em 3.2 × 10 -28 Joule and δω em 2.2 × 10 -28 Joule, respectively. Upon different current directions in DC current stressing, there is a counteractive or accelerated effect between TM and EM on Zn migration, resulting different microstructures at the cathode side in the solder joints. © 2010 Springer Science+Business Media, LLC.

Jiang J.,Shennan Circuits Co. | Li G.,Shennan Circuits Co. | Yang Z.,Shennan Circuits Co. | Ding P.,Shennan Circuits Co.
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

Finite element models of heat spreader enhanced plastic ball grid array (EPBGA) packages with different structures, materials and process treatments had been developed in this study. Predicted result indicated that the difference of stress were not significant generated in the structures with single-layer and double-layer spreader respectively. The stress became smaller gradually with the increasing of glue thickness. Moreover, the encapsulation material of CV5420 brought less stress for package than FP4654. The result of reliability test revealed that product using the spreader dealt with ENEPIG all failed after reflowed three times, which had the worst reliability. Plasma proved beneficial to the reliability of package. The performance of 2200 was better than that of 2100A and 2300. Finally, the optimal structure design and material collocation were achieved for the EPBGA package. © 2015 IEEE.

Yang Z.,Shennan Circuits Co. | Gunawan F.,Shennan Circuits Co. | Gu X.,Shennan Circuits Co. | Ding K.,Shennan Circuits Co. | He H.,Aviation Industry Corporation of China
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

Recently, Embedded Components in Substrates (ECiS) technology has been developed with many technologies. Some of these technologies are very mature and compatible for any conventional processes of PCB/Substrate manufacturing which need to be supported by SMT processes. Nowadays, some of electronic products with ECiS technologies already got high volume production scale. As frontline, this paper will describe about the classification of these ECiS technologies. As the development of ECiS technologies into the 3D stacking generation, there are 3 major options had been researched and developed by the industry. One of the options uses a combined process of two different ECiS technologies (via technique and vialess technique) as a new solution which will provide more possibility to decrease the size of the Integrated Circuit Products with more complexly system integration, much higher reliability and more simply interconnection, all these will dramatically improve the electrical performance. By combining the advantages of via technique and via-less technique, an optimized technique has been developed for the ECiS technology. We designed test boards with daisy chain die and the manufacturing process is demonstrated as follow. A specific requirement for Pad metallization of dies was prepared with RDL technique firstly, after that one of the dies was embedded with blind via technique and then followed solder joint technique for the other die to accomplish the stacking process completely. This thin test board structure with embedded 2 stacking dies and very short path for interconnection between the stack dies would be discussed with more details in last section of this paper. At last, some key reliability test items (such as Moisture Sensitivity Test in Level 3 with 5 times Assembly Rework and Thermal Cycling Test) were applied to analyze the reliability of these test boards in details. Also the electrical test and Scanning Acoustic Microscope (SAM) for both before and after the reliability test showed very good results. © 2015 IEEE.

Gu X.,Shennan Circuits Co. | Yung K.C.,Hong Kong Polytechnic University
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

A simple and facile camera flash sintering method has been developed to sinter the ink-jet printed silver nanoparticle traces at room temperature to form conductive circuit on flexible polymer substrates. The electrical resistivity of silver traces sintered by two times of camera flash can be decreased to 8.4 μΩ cm, which is only about 1/3 that of the silver tracks thermally sintered at 150 °C for 80min. As camera flash sintering is fast, simple and cost-effective, it is promising to be widely used for nanoink-jet printed electronics. Furthermore, this method is expected be readily generalized to prepare other types of metal lines on various substrates such as glass and polymer owing to the room temperature process. The sintering mechanism is also investigated via in-situ recording temperature of the Ag nanoparticles based track during the flash sintering, which confirms the enhanced photothermal effect of nanostructures. © 2015 IEEE.

Yang Z.,Shennan Circuits Co. | Li S.,Shennan Circuits Co. | Gu X.,Shennan Circuits Co. | Huang D.,Shennan Circuits Co.
16th International Conference on Electronic Packaging Technology, ICEPT 2015 | Year: 2015

Package on Package (PoP) is a widely used high density package solution for package stacking technology in various device applications. Normally, the top package will connect to the bottom package by solder ball with several hundred micrometer diameter. The I/O number will be limited due to the solder ball will collapse during the reflow. In this study, a copper pillar with diameter of 200μm and height of 150-180μm will be used to replace the solder ball. With the structure of copper pillar, only a very small volume of solder will be used for the joint to connect the top and bottom package. In this paper, the finite element Modeling (FEM) simulation will be used to calculate the temperature distribution in the new PoP package with copper pillar. Also, the Cu pillar/solder joint microstructure evolution will be studied in several reliability tests, including 500 cycles temperature cycling test (TCT) and high temperature storage test (HTST) at 150°C with 500h. © 2015 IEEE.

Jing J.,Shennan Circuits Co. | Lingwen K.,Shennan Circuits Co.
Proceedings - 2010 11th International Conference on Electronic Packaging Technology and High Density Packaging, ICEPT-HDP 2010 | Year: 2010

With the rapid development of high-speed digital circuits and high-integration-chip technology, more high-speed signals need to be transferred in high-speed interconnection. However, high-speed signals will experience delay, reflection, attenuation and crosstalk during the transferring. The transmission characteristic of printed circuit board (PCB) is very important as PCB is the support for the whole circuit systems. As the signal integrity is very critical for the electronic products, both designers of high-speed circuit and PCB manufactures focus on solving the signal integrity problem. Signal integrity in high-speed circuit design is very important. In this study, discontinuous ground and the via hole signal integrity analysis in the PCB level were carried out on the basis of transmission lines. Based on the results of the experiments, guidelines for design and manufacturing process were proposed to improve the signal integrity problem. With the rapid development of electronic technology, largescale and super large-scale integrated circuits are used in the systems. The size of the Integrate circuits chip is smaller and smaller, and the I/0 amount is more and more according to the package type of integrate circuits chip. And the speed of the signal is more and more fast with the development of the integrate circuits process. How to deal with the high-speed signal becomes the key while engineers design the circuits because of the smaller size of the electronic design, the higher density of the circuit layout, and the higher and higher frequency of the signal. With the rapid development of highspeed digital circuits and high-integration-chip technology, influence of the transmission line and delamination characteristic on system electronical performance is more and more important. Therefore, high speed system design need to solve signal integrity problems of delay .crosstalk and transmission line effect, and so on. The influence of the high-speed interconnection on signal integrity includes two parts.Firstly, delay, reflection, and crosstalk effect of transmission line because of the impedance mismatch, discontinuous interconnection. Secondly, isochronous Switching Noise (SSN), for some circuits sharing the ground or feeder with the EMC. The first part was carried out in this article. © 2010 IEEE.


Shennan Circuits Co. | Date: 2012-01-16

Computer chips; integrated circuits; printed circuits.

Shennan Circuits Co. | Date: 2012-05-18

A package structure and a packaging method thereof are provided, in which an inductor is integrated into a substrate so as to save a packaging space and thus improve the integration level and packaging effect of the system. The package structure includes a substrate, wherein a first metal enclosing structure and a second metal enclosing structure are provided on the substrate and are connected through a connecting hole in the substrate so as to form a helical

A printed circuit board (PCB) a method for processing PCB and an electronic apparatus are provided. The method for processing PCB may include: forming a hole in the PCB, wherein the PCB includes a metal matrix and at least two substrate layers, at least one of the at least two substrate layers has an geoelectric layer thereon; the metal matrix is fixed in a slot provided its the substrate, the formed hole contacts with both the geoelectric layer and the metal matrix; and providing conductive substances in the hole, with the conductive substances in the hole being in contact with the inner geoelectric layer and the metal matrix, so that the inner geoelectric layer and the metal matrix are in conduction with each other. The solutions of the embodiments of the application are beneficial to improve reliability of connection between the geoelectric layer and the metal matrix of the PCB, and improve transmission performance of a high frequency signal.

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