Shanghai Simgui Technology Co.

Shanghai, China

Shanghai Simgui Technology Co.

Shanghai, China

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Chang Y.,CAS Shanghai Institute of Microsystem and Information Technology | Chang Y.,Shanghai Simgui Technology Co. | Xue Z.,CAS Shanghai Institute of Microsystem and Information Technology | Chen D.,Ningbo University | And 9 more authors.
Journal of Vacuum Science and Technology B: Nanotechnology and Microelectronics | Year: 2016

High-quality strain-relaxed extremely thin silicon-on-insulator (ETSOI) has been fabricated by using H-trapping and etch-stop process in the H-implanted Si/Si0.70Ge0.30/Si/B-doped Si0.70Ge0.30/Si heterostructure. Compared to conventional ion-cut process, the combination of ultrathin SiGe interlayer with boron doping can significantly decrease the critical hydrogen implantation dosage needed for layer transfer by improving H-trapping efficiency. During subsequent annealing process, implanted H preferentially agglomerates at the trapping centers and induces long microcracks at the B-doped Si0.70Ge0.30/Si interface as well as in the near-interface region. The selective etch-stop process was used to remove residual Si/SiGe layers to expose a strain-relaxed Si device layer with a smooth surface morphology. These results demonstrate facilitated ion-cut as a promising approach for fabricating high crystalline quality ETSOI substrate and further offer a potential solution for scaling planar complementary metal-oxide-semiconductor to 22 nm node and beyond. © 2016 American Vacuum Society.


Wei X.,CAS Shanghai Institute of Microsystem and Information Technology | Wei X.,Shanghai Simgui Technology Co. | Wu A.,CAS Shanghai Institute of Microsystem and Information Technology | Wang X.,Shanghai Simgui Technology Co. | And 10 more authors.
Journal of Vacuum Science and Technology B: Microelectronics and Nanometer Structures | Year: 2010

In this article, silicon on insulator (SOI) was fabricated by separation by implanted oxygen (SIMOX) layer transfer process. The thickness uniformity of the top Si (superficial Si of the SOI) evaluated by spectroscopic ellipsometry remains constant through the etch-stop thinning process. A defect-free top Si was observed by transmission electron microscopy, as well as its atomic-scale sharp interface that was adjacent to the buried oxide (BOX) layer. The top Si/BOX interface properties, including upper BOX surface roughness and interface state density, were investigated by atomic force microscopy (AFM) and pseudo-metal-oxide-semiconductor method, respectively. In addition, the surface morphology of the square pit and square hole defect of the top Si were observed. Using AFM, it is found that the morphology depends on the top Si/BOX interface morphology of the donor wafer and can be improved by optimizing the annealing process. The square hole defect caused by anisotropic etching is discussed in detail, and it is proven to originate from the defects in the SIMOX BOX. © 2010 American Vacuum Society.


Wei X.,CAS Shanghai Institute of Microsystem and Information Technology | Wu A.,CAS Shanghai Institute of Microsystem and Information Technology | Weng X.,Shanghai Simgui Technology Company Ltd | Li X.,Shanghai Simgui Technology Company Ltd | And 8 more authors.
Journal of the Electrochemical Society | Year: 2010

In this paper, two approaches combining the separation by implanted oxygen layer transfer (SLT) process with Si epitaxy are proposed to fabricate a silicon-on-insulator (SOI) wafer. Spectroscopic ellipsometry indicates that SOI wafers with the top Si layers of 1491.46 ± 14.9 and 1476.44 ± 18.5 nm are obtained. Defect-free top Si as well as atomic-scale sharp top Si/buried oxide interfaces are observed by transmission electron microscopy, indicating a high crystal quality and a perfect structure of the SLT SOI wafers. Using atomic force microscopy, the surface and top Si/buried oxide interface morphology of the SLT SOI wafers is also investigated. © 2009 The Electrochemical Society.


Liu X.,CAS Shanghai Institute of Microsystem and Information Technology | Liu X.,University of Chinese Academy of Sciences | Ma X.,CAS Shanghai Institute of Microsystem and Information Technology | Ma X.,University of Chinese Academy of Sciences | And 6 more authors.
Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics | Year: 2010

A modified postannealing at 1000 °C in N2 ambient has been carried out to improve the Ge distribution in the SiGe layer fabricated by the Ge condensation process, which is a potential technique for strained Si fabrication. Three kinds of SiGe-on-insulator samples have been fabricated by so-called Ge condensation, which is the oxidation of the SiGe layer on an insulator to enhance the Ge fraction. After different postannealing processes and the necessary cleaning steps, 20-nm-thick strained Si films are epitaxially grown on them. Though the differences of surface topography among the three samples are not great, the one with the modified postannealing process has the most uniform Ge element distribution and the least misfit dislocations. Meanwhile, the strain values obtained by Raman spectra are coherent with the Ge fraction in SiGe near the Si/SiGe interface and the sample with the modified postannealing process has a larger strain value than the one with a conventional postannealing. The performance of metal-oxide-semiconductor field-effect transistors, based on the strained Si samples here, shows a significant enhancement, compared to those based on Si and Si on insulator samples. © 2010 American Vacuum Society.


Patent
CAS Shanghai Institute of Microsystem, Information Technology and Shanghai Simgui Technology Co. | Date: 2010-07-10

A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.


Patent
Shanghai Simgui Technology Co., CAS Shanghai Institute of Microsystem and Information Technology | Date: 2012-06-06

A method for forming an edge-chamfered substrate with a buried insulating layer is provided, which comprises the following steps: providing a first substrate (S10); forming an etching mask layer on surfaces of the first substrate, wherein said etching mask layer is formed on the whole surfaces of the first substrate (S11); chamfering a glazed surface of the first substrate and the etching mask layer thereon by the edge grinding (S12); by rotary etching, etching the first substrate which is exposed by the edge grinding on the etching mask layer (S13); providing a second substrate (S14); and bonding the first substrate to the second substrate with a buried insulating layer (S15). The method avoids the edge collapses and the changes of the warp degree in subsequent processes.


Patent
Shanghai Simgui Technology Co. | Date: 2016-05-23

Disclosed are a low-warpage semiconductor substrate and a method for preparing the same. The method includes: providing a first substrate and a second substrate, the first substrate comprising a first surface and a second surface which are opposite to each other, the first surface being provided with a first insulating layer. A second insulating layer is dispose on the second surface. A support layer is disposed on the second substrate. An oxidation layer is arranged on a surface of the support layer and a device layer is arranged on a surface of the oxidation layer. The method further includes bonding the first substrate and the second substrate; and forming a passivation layer on a surface of the second insulating layer by epitaxy, where the second insulating layer and the passivation layer are configured to adjust warpage of the semiconductor substrate.


Patent
Shanghai Simgui Technology Co. | Date: 2016-05-23

A method is provided for preparing a semiconductor substrate with smooth edges. The method includes: providing a first substrate and a second substrate; forming an insulating layer on a surface of the first substrate and/or the second substrate; bonding the first substrate and the second substrate by using the insulating layer as an intermediate layer; conducting a chamfering process on the bonded first substrate and insulating layer; and conducting edge polishing on the first substrate and insulating layer subjected to the chamfering process.


A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded.


Patent
Shanghai Simgui Technology Co. | Date: 2016-05-23

Disclosed is a method for preparing a low-warpage semiconductor substrate. The method includes: providing a first substrate and a second substrate, the first substrate including a first surface and a second surface which are opposite to each other, a first insulating layer is disposed on the first surface. A second insulating layer is disposed on the second surface. The second substrate includes a support layer, an oxidation layer arranged on a surface of the support layer, and a device layer arranged on a surface of the oxidation layer. The method further includes bonding the first substrate and the second substrate by using the device layer and the first insulating layer as an intermediate layer; and forming a passivation layer on a surface of the second insulating layer by means of adhesion, where the second insulating layer and the passivation layer are configured to adjust warpage of the semiconductor substrate.

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