Entity

Time filter

Source Type

Shanghai, China

Zhong M.,Fudan University | Zhong M.,Shanghai Randnter Ltd. | Chen S.M.,Shanghai Randnter Ltd. | Zhang D.W.,Fudan University
Journal of Nanomaterials | Year: 2015

Embedded SiGe (eSiGe) source/drain (S/D) was studied to enhance PMOS performance. Detailed investigations concerning the effect of GeHand Bgas flow rate on the resultant Boron-doping of the SiGe layer (on a 40 nm patterned wafer) were carried out. Various SiGeB epitaxial growth experiments were realized under systematically varying experimental conditions. Key structural and chemical characteristics of the SiGeB layers were investigated using Secondary Ion Mass Spectroscopy (SIMS), nanobeam diffraction mode (NBD), and Transmission Electron Microscopy (TEM) itself. Furthermore, I on / I off performances of 40 nm PMOS transistors are also measured by the Parametric Test Systems for the semiconductor industry. The results indicate that the ratio between GeHand Bgas flow rates influences not only the Ge and Boron content of the SiGeB layer, but also the PMOS channel strain and the morphology of the eSiGe S/D regions which directly affect PMOS performance. In addition, the mechanism of Boron-doping during SiGe layer growth on the pattern wafer is briefly discussed. The results and discussion presented within this paper are expected to contribute to the optimization of eSiGe stressor, aimed for advanced CMOS devices. © 2015 Min Zhong et al. Source


Zhong M.,Fudan University | Zhong M.,Shanghai Randnter Ltd. | Zhao Y.H.,Shanghai Randnter Ltd. | Chen S.M.,Shanghai Randnter Ltd. | And 3 more authors.
Key Engineering Materials | Year: 2015

An embedded SiGe layer was applied in the source/drain areas (S/D) of a field-effect transistor to boost the performance in the p channels. Raised SiGe S/D plays a critical role in strain engineering. In this study, the relationship between the SiGe overfilling and the enhancement of channel stress was investigated. Systematic technology computer aided design (TCAD) simulations of the SiGe overfill height in a 40 nm PMOS were performed. The simulation results indicate that a moderate SiGe overfilling induces the highest stress in the channel. Corresponding epitaxial growth experiments were done and the obtained experimental data was in good agreement with the simulation results. The effect of the SiGe overfilling is briefly discussed. The results and conclusions presented within this paper might serve as useful references for the optimization of the embedded SiGe stressor for 40 nm logic technology node and beyond. © (2015) Trans Tech Publications, Switzerland. Source

Discover hidden collaborations