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Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-22

A dual-port SRAM timing control circuit, with three NMOS transistors connected in series respectively between ground and nodes of the two bit lines to which the cell structure corresponds. The gates of the NMOS transistors are connected to a corresponding wordline, a pulse signal and a timing control signal, respectively. The each pulse signals are formed by a corresponding clock signal inputted into a first pulse generator, respectively. An address signal, after passing through an address latch, is inputted into an address comparator for comparison, with the address comparison result outputted to a timing control signal generator; and the pulse signal, after undergoing an AND operation, is inputted into the timing control signal generator, with a timing control signal outputted. When the two address signals are the same, the address comparison result is 1; when the two address signals are not the same, the address comparison result is 0; when the AND result of the two pulse signals is 0, the timing control signal is 1; when the AND result of the two pulse signals is 1, the timing control signal is an inverting signal of the address comparison result. The present invention can reduce the operational power consumption of SRAM without affecting the read reliability.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-21

A circuit for control of time for read operation is disclosed which additionally incorporates a dummy device circuit and a dummy sensitive amplifier circuit, uses a current mirror circuit to mirror a reference current in a reference device circuit into the dummy device circuit to generate a mirrored current, and generates time control signals based on the mirrored current. Due to the same adaptation of the mirrored current to the size of a test device as the reference current, the time control signals are also adapted to the size of the test device. This addresses the problem of fixed time control signals arising from the use of a conventional RC relay circuit and enables the time control signals to change with the size of the test device as well as Process Voltage Temperature, thereby resulting in an effective reduction in average energy consumed in read operation.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-21

An ESD protection circuit is disclosed, in which an RC trigger circuit and a transmission gate are used for determination of ESD protection triggering, and a silicon-controlled rectifier for ESD current conductance. The RC trigger circuit and the transmission gate allow improved trigger efficiency. In addition, the silicon-controlled rectifier incorporates first and second resistors, which can be implemented to have very low resistance values and are therefore able to effectively prevent the occurrence of latch-up during normal operation, as well as pull-up and pull-down transistors which can make an additional contribution to latch-up inhibition when turned on.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-29

A high voltage LDMOS device having high side source voltage, an n type buried layer and a p type buried layer situated on the interface between a p type substrate and an n type epitaxial layer; a lateral surface of the n type buried layer and a lateral surface of the p type buried layer not in contact, and are distant from one another with a distance, thereby increasing the withstand voltage between the n type buried layer and the p type buried layer; the p type buried layer and the drain overlap at least partially in a vertical direction, enabling the p type buried layer to exert a reduced surface field action on the drain, to increase the withstand voltage of the drain against the source; the source and the body terminal centrally on top of the n type buried layer.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-22

A memory testing circuit and method are disclosed, the redesigning of a memory to be tested through incorporation therein a testing circuit includes a self-test circuit incorporating a decoder circuit, and a VPPIO I/O module incorporating an encoder circuit and having multiple functions including digital I/O, high analog voltage I/O and current I/O. An oscillator module embedded in the multiplexer circuit provides a clock signal for the testing. The VPPIO I/O module is configured to convert, by the self-test circuit, a stimulating input from a single signal pin to a parallel signal recognizable by the memory and an analog voltage/current signal, thereby accomplishing proper testing of the memory. This enables a single signal pin to test all functions of one memory, thereby increasing the number of memory dies on a wafer tested in parallel by a test instrument and reducing the testing time per wafer as well as testing cost.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-08

A built-in self-test (BIST) circuit is disclosed which integrates the functions of pins for test input data TDI, test output data TDO and an analog input signal VPP into a single digital/analog input/output module, and internally produces a test trigger signal STROBE and a digital-analog conversion signal ANA. In addition, when there is a need to power the test chip with a voltage or current, a data generation circuit of the BIST circuit can generate a digital-analog conversion signal to change an operating mode of the digital/analog input/output module and hence enable the transmission of analog data. According to the present invention, the testing can be performed with only two pins, which leads to an improvement in test efficiency and a reduction in test cost.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-29

An NLDMOS device that includes a drift region, a P well, and a first PTOP layer and a second PTOP layer formed on the drift region, wherein the first PTOP layer has the same lateral size with the second PTOP layer, the first PTOP layer is spaced from the second PTOP layer in the longitudinal direction and located on the bottom of the second PTOP layer, with the depth of the first PTOP layer less than or equal to that of the bottom of the P well. The present invention also discloses a method for manufacturing the NLDMOS device.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-06-10

The present invention discloses a resistor circuit with temperature coefficient compensation, which comprises a first series resistor composed of a first resistor and a second resistor interconnected in series, and a second parallel resistor composed of a third resistor and a fourth resistor interconnected in series, with the first series resistor and the second parallel resistor interconnected in series, wherein the first resistor and the second resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the first series resistor offset each other, and the third resistor and the fourth resistor respectively have a positive and negative temperature coefficient and make the positive and negative temperature coefficients of the second parallel resistor offset each other. A secondary temperature coefficient compensation function is provided between the first series resistor and the second parallel resistor of the present invention, which can make the resistor circuit keep the temperature coefficient compensation function in any combination of process corner variations and able to achieve the high-precision resistance at any process corners.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-21

A programming verification control circuit is disclosed, including: a first decoder circuit for decoding a word line of a memory bit; a first drive circuit for receiving a first voltage and providing the first voltage to the word line of the memory bit based on a decoding result of the first decoder circuit; a second decoder circuit for decoding a control gate of the memory bit; a second drive circuit for receiving a second voltage and providing the second voltage to the control gate of the first memory bit based on a decoding result of the second decoder circuit; and a voltage equalizer for receiving the first voltage, the second voltage and a first enable signal and, in event of the first enable signal being valid, controlling the first voltage and the second voltage to be conducted. A method for controlling the programming verification control circuit is also disclosed.


Patent
Shanghai Huahong Grace Semiconductor Manufacturing Corporation | Date: 2015-12-21

A boost capacitor circuit is disclosed which includes a first nMOS transistor and a voltage doubler circuit including: a first pMOS transistor having a drain coupled to a working voltage, a source coupled to a first node and a gate coupled to a second node; a drive inverter having an input terminal for receiving a first signal; a second pMOS transistor having a gate coupled to an output terminal of the drive inverter, a source and a drain coupled to each other and further to the first node; a third pMOS transistor having a gate for receiving the first signal, a source coupled to the first node and a drain coupled to the second node; and a second nMOS transistor having a gate for receiving the first signal, a source coupled to a low voltage and a drain coupled to the second node.

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