Shanghai Hua Hong NEC Electronics Company

Shanghai, China

Shanghai Hua Hong NEC Electronics Company

Shanghai, China
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Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-09-05

A super-junction device including a unit region is disclosed. The unit region includes a heavily doped substrate; a first epitaxial layer over the heavily doped substrate; a second epitaxial layer over the first epitaxial layer; a plurality of first trenches in the second epitaxial layer; an oxide film in each of the plurality of first trenches; and a pair of first films on both sides of each of the plurality of first trenches, thereby forming a sandwich structure between every two adjacent ones of the plurality of first trenches, the sandwich structure including two first films and a second film sandwiched therebetween, the second film being formed of a portion of the second epitaxial layer between the two first films of a sandwich structure. A method of forming a super-junction device is also disclosed.


Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-05-22

A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions.


Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-06-06

An ultra-high voltage silicon-germanium (SiGe) heterojunction bipolar transistor (HBT), which includes: a P-type substrate; an N-type matching layer, a P-type matching layer and an N collector region stacked on the P-type substrate from bottom up; two field oxide regions separately formed in the N collector region; N+ pseudo buried layers, each under a corresponding one of the field oxide regions and in contact with each of the N-type matching layer, the P-type matching layer and the N collector region; an N+ collector region between the two field oxide regions and through the N collector region and the P-type matching layer and extending into the N-type matching layer; and deep hole electrodes, each in a corresponding one of the field oxide regions and in contact with a corresponding one of the N+ pseudo buried layers. A method of fabricating an ultra-high voltage SiGe HBT is also disclosed.


Patent
SHANGHAI HUA HONG NEC Electronics CO | Date: 2013-08-12

A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate, a p-type epitaxial layer, a p-type well, a lightly doped n-type drain region, a gate oxide layer, a polysilicon gate, a dielectric layer and a Faraday shield. The Faraday shield includes: a horizontal portion covering a portion of the polysilicon gate and isolated from the polysilicon gate by the dielectric layer; a step-like portion with at least two steps covering a portion of the lightly doped n-type drain region and isolated from the lightly doped n-type drain region by the dielectric layer; and a vertical portion connecting the horizontal portion with the step-like portion and isolated from the polysilicon gate and the lightly doped n-type drain region by the dielectric layer. A method of fabricating such an RF LDMOS device is also disclosed.


Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-07-22

An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and being formed in the substrate; a doped region having the first type of conductivity and being formed in the substrate, the doped region being located at a first end of the drift region and laterally adjacent to the drift region; and a heavily doped drain region having the second type of conductivity and being formed in the substrate, the heavily doped drain region being located at a second end of the drift region, wherein the drift region has a step-like top surface with at least two step portions, and wherein a height of the at least two step portions decreases progressively in a direction from the doped region to the drain region. A method of fabricating LDMOS device is also disclosed.


Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-08-16

A semiconductor device includes: a P+ substrate; a P epitaxial layer over the P+ substrate; a P-well and an N drift region in the P epitaxial layer and laterally adjacent to each other; an N+ source region in the P-well and connected to a front-side metal via a first contact electrode; an N+ drain region in the N drift region and connected to the front-side metal via a second contact electrode; a gate structure on the P epitaxial layer and connected to the front-side metal via a third contact electrode; and a metal plug through the P epitaxial layer and having one end in contact with the P+ substrate and the other end connected to the front-side metal, the metal plug being adjacent to one side of the N+ source region that is farther from the N drift region. A method for fabricating the semiconductor device is also disclosed.


Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-08-19

An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and a doped region having the first type of conductivity both formed in the substrate; a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farther from the doped region; and a buried layer having the first type of conductivity and being formed in the drift region, the buried layer being in close proximity to the drain region and having a step-like bottom surface, and wherein a depth of the buried layer decreases progressively in a direction from the drain region to the doped region. A method of fabricating LDMOS device is also disclosed.


Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-01-30

A method of preventing dopant from diffusing into atmosphere in a BiCMOS process is disclosed. The BiCMOS process includes the steps of: depositing a first silicon oxide layer and a silicon nitride layer over surface of a silicon substrate; etching the silicon substrate to form a plurality of shallow trenches therein; depositing a second silicon oxide layer over surface of the silicon substrate and forming silicon oxide sidewalls over inner side faces of each of the plurality of shallow trenches; forming a heavily doped pseudo buried layer under a bottom of one of the plurality of shallow trenches by implanting a dopant with a high concentration; performing an annealing process to promote diffusion of the dopant contained in the pseudo buried layer, wherein the method includes growing, by thermal oxidation, a silicon oxide layer over a bottom of each of the plurality of shallow trenches during the annealing process.


Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-09-19

An optical fiber clamp and fabrication method thereof are disclosed. The optical fiber clamp includes one or more clamp units. Each clamp unit includes a clamp body formed of silicon, a guide hole formed under a top surface of the clamp body, the guide hole having an upper diameter greater than a lower diameter of the guide hole and having an inclined sidewall; and a locating hole connected to and extends downward from a bottom of the guide hole through the clamp body, the locating hole having an upper diameter equal to a lower diameter of the locating hole and smaller than the lower diameter of the guide hole.


Patent
Shanghai Hua Hong Nec Electronics Co. | Date: 2013-03-15

A digital correction circuit for a pipelined analog-to-digital converter (ADC) is disclosed. Compared to the conventional digital correction circuit which uses adders to perform operations in ADC digital correction part and hence needs a rather long operation time, the digital correction circuit of this invention can reduce the time needed in operations in the finial digital correction circuits and thus can optimize operation time, by allocating the operations to a plurality of pipeline stages of second sub-circuits configured to synchronize digital codes, each of which can perform part of the operations only with NAND gates, NOR gates, phase inverters and D-type flip-flops, without needing to use adders.

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