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Roxhed N.,KTH Royal Institute of Technology | Niklaus F.,KTH Royal Institute of Technology | Fischer A.C.,KTH Royal Institute of Technology | Forsberg F.,KTH Royal Institute of Technology | And 8 more authors.
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2010

Cost efficient integration technologies and materials for manufacturing of uncooled infrared bolometer focal plane arrays (FPA) are presented. The technology platform enables 320x240 pixel resolution with a pitch down to 20 μm and very low NETD. A heterogeneous 3D MEMS integration technology called SOIC (Silicon-On-Integrated-Circuit) is used to combine high performance Si/SiGe bolometers with state-of-the-art electronic read-out-integrated-circuits. The SOIC integration process consists of: (a) Separate fabrication of the CMOS wafer and the MEMS wafer. (b) Adhesive wafer bonding. (c) Sacrificial removal of the MEMS handle wafer. (d) Via-hole etching. (e) Via formation and MEMS device definition. (f) Sacrificial etching of the polymer adhesive. We will present an optimized process flow that only contains dry etch processes for the critical process steps. Thus, extremely small, sub-micrometer feature sizes and vias can be implemented for the infrared bolometer arrays. The Si/SiGe thermistor is grown epitaxially, forming a mono-crystalline multi layer structure. The temperature coefficient of resistance (TCR) is primarily controlled by the concentration of Ge present in the strained SiGe layers. TCR values of more than 3%/K can be achieved with a low signal-to-noise ratio due to the mono-crystalline nature of the material. In addition to its excellent electrical properties, the thermistor material is thermally stable up to temperatures above 600 °C, thus enabling the novel integration and packaging techniques described in this paper. Vacuum sealing at the wafer level reduces the overall costs compared to encapsulation after die singulation. Wafer bonding is performed using a Cu-Sn based metallic bonding process followed by getter activation at ≥350 °C achieving a pressure in the 0.001 mbar range. After assembling, the final metal phases are stable and fully compatible with hightemperature processes. Hermeticity over the product lifetime is accomplished by well-controlled electro-deposition of metal layers, optimized bonding parameters and a suitable bond frame design. © 2010 Copyright SPIE - The International Society for Optical Engineering.


Forsberg F.,KTH Royal Institute of Technology | Lapadatu A.,Sensonor AS | Kittilsland G.,Sensonor AS | Martinsen S.,Sensonor AS | And 11 more authors.
IEEE Journal on Selected Topics in Quantum Electronics | Year: 2014

We demonstrate infrared focal plane arrays utilizing monocrystalline silicon/silicon-germanium (Si/SiGe) quantum-well microbolometers that are heterogeneously integrated on top of CMOS-based electronic read-out integrated circuit substrates. The microbolometers are designed to detect light in the long wavelength infrared (LWIR) range from 8 to 14 μm and are arranged in focal plane arrays consisting of 384 × 288 microbolometer pixels with a pixel pitch of 25 μm × 25 μm. Focal plane arrays with two different microbolometer designs have been implemented. The first is a conventional single-layer microbolometer design and the second is an umbrella design in which the microbolometer legs are placed underneath the microbolometer membrane to achieve an improved pixel fill-factor. The infrared focal plane arrays are vacuum packaged using a CMOS compatible wafer bonding and sealing process. The demonstrated heterogeneous 3-D integration and packaging processes are implemented at wafer-level and enable independent optimization of the CMOS-based integrated circuits and the microbolometer materials. All manufacturing is done using standard semiconductor and MEMS processes, thus offering a generic approach for integrating CMOS-electronics with complex miniaturized transducer elements. © 2014 IEEE.


Grant
Agency: Cordis | Branch: FP7 | Program: CP | Phase: ICT-2009.3.9 | Award Amount: 15.49M | Year: 2010

Best-Reliable Ambient Intelligent Nanosensor Systems e-BRAINS represent a giant leap for outstanding future applications in the area of ambient living with the ultimate need for integration of heterogeneous technologies, high-performance nanosensor devices, miniaturization, smart wireless communication and best-reliability.\ne-BRAINS with minimum volume and weight as well as reduced power consumption can be utilized in ambient living systems. Successful market entry of such innovative ambient intelligence products will be determined by the performance improvement achieved and the cost advantage in relation to the total system cost.\nThe basic requirement for robustness and reliability of the heterogeneous integration technologies and the nanosensor layers is in the focus of all e-BRAINS developments.\nThe designated nanosensor systems represent a very promising innovative approach with the potential to enable high-performance and precise functions in new products. The application of nanotechnology will allow large improvements in functionality and will open a wide range of applications for European companies.\nFuture e-BRAINS applications require significantly higher integration densities. Performance, multi-functionality and reliability of such complex heterogeneous systems will be limited mainly by the wiring between the subsystems. Suitable 3D integration technologies create a basis to overcome these drawbacks with the benefit of enabling minimal interconnection lengths. In addition to enabling high integration densities, 3D integration is a very promising cost-effective approach for the realization of heterogeneous systems.\nBesides the heterogeneous system integration the main criteria of e-BRAINS is the need for miniaturized energy storage/delivery systems, low power consumption, smart communication and methodology for reliability and robustness.\ne-BRAINS benefits from the established European 3D technology platform as major result of the IP e-CUBES.


Grant
Agency: Cordis | Branch: FP7 | Program: CP-FP | Phase: SPA.2012.3.1-01 | Award Amount: 1.87M | Year: 2013

Fueled by mass market demand, terrestrial consumer electronics continue to drive technology advancement in the field of microelectronics devices. Many of these technologies are spearheaded by the contributions of Small and Medium Enterprise (SME). There is a clear opportunity to revolutionize space technologies by leveraging advancement in the commercial electronics market. However, despite the obvious benefits to the space industry, it remains difficult for SMEs to get involved due to the significant cost, effort, time, and paper work to qualify parts for space applications. A trend toward smaller and cheaper satellites allows for a novel approach to space qualification and testing. Nanosatellites (between 1kg and 10kg) can be launched at a relatively low cost as piggy back payloads for larger satellite missions. Since the cost of failure is an order of magnitude lower than conventional satellites, nanosatellites offer an ideal platform for high risk demonstration missions. The aim of this project is to flight qualify a wide range of SME payloads in a 3U 3kg nanosatellite platform operating at a 700km orbit. The primary purpose of this spacecraft is as a technology demonstrator. Each SME in the consortium will be responsible for contributing a particular spacecraft subsystem. The University of Surrey will integrate these systems into the nanosatellite platform, and will also be responsible for the ADCS and CMGs of the satellite. ISIS will oversee the launch opportunity and deployment of the satellite. Astrium, as a Large System Integrator (LSI), will help roadmap the technology demonstrated in this mission to future applications within the European space framework.


Forsberg F.,KTH Royal Institute of Technology | Roxhed N.,KTH Royal Institute of Technology | Fischer A.C.,KTH Royal Institute of Technology | Samel B.,Acreo Ab | And 7 more authors.
Infrared Physics and Technology | Year: 2013

Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of -3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu-Sn solid-liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications. © 2013 Elsevier Ltd. All rights reserved.


Roer A.,Sensonor AS | Lapadatu A.,Sensonor AS | Wolla E.,Sensonor AS | Kittilsland G.,Sensonor AS
Proceedings of SPIE - The International Society for Optical Engineering | Year: 2013

An uncooled microbolometer with peak responsivity in the long wave infrared region of the electromagnetic radiation is developed at Sensonor AS. It is a 384×288 focal plane array with a pixel pitch of 25μm, based on monocrystalline Si/SiGe quantum wells as IR sensitive material. The high sensitivity (TCR) and low 1/f-noise are the main performance characteristics of the product. The frame rate is maximum 60Hz and the output interface is digital (LVDS). The quantum well thermistor material is transferred to the read-out integrated circuit (ROIC) by direct wafer bonding. The ROIC wafer containing the released pixels is bonded in vacuum with a silicon cap wafer, providing hermetic encapsulation at low cost. The resulting wafer stack is mounted in a standard ceramic package. In this paper the architecture of the pixels and the ROIC, the wafer packaging and the electro-optical measurement results are presented. © 2013 SPIE.


Keller C.,Infineon Technologies | Tus S.,SensoNor AS
Microelectronics Reliability | Year: 2010

In this case study we present the failure analysis flow of a MEMS device. Because of the combination of a MEMS sensor and ASIC die within one package (system in package) new materials are used. This causes new failure modes and creates particular failure analysis challenges. In this particular case study, contamination due to glob top on the ASIC die causes reliability problems. The change of mechanical stress within the package then leads to open bonds causing functional fails in the field application. To determine the root cause of the problem multiple steps of selective decapsulation are necessary as shown in this study in detail. © 2010 Elsevier Ltd. All rights reserved.


Grant
Agency: Cordis | Branch: FP7 | Program: JTI-CS | Phase: JTI-CS-2010-2-SFWA-01-022 | Award Amount: 800.00K | Year: 2010

The subject of this proposal is the design of a MEMS gyroscope for SFWA purposes. This is a high-end application, stemming from its noise and stability requirements. We will not develop a completely novel device, i.e. with entirely new design principles, fabrication processes, etc. On the contrary, the performance of Sensonors existing, qualified high-end product STIM202 is very close to the targeted specification. Thus, the improvement of a rather limited number of technical issues is required to satisfy the specification. STIM202 is a 1, 2 or 3 axes gyroscope. It meets this Calls specification in noise and short term stability. Long term stability is also very good, while an effort remains to establish those design and technology improvements that are needed to explicitly make the sensor fulfill the SFWA specification. The route to attain this goal is the focus of this proposal. Sensonors long track record in MEMS places the company in a unique position in extreme reliability silicon MEMS. More than 2 million MEMS gyros, 250 million MEMS accelerometers, and 250 million MEMS pressure sensors designed and manufactured by Sensonor have been shipped, with an impressive field failure rate of less than 0.1ppm. This is ultimate proof of the extreme reliability achievable in silicon MEMS by Sensonor. In the project, we will identify and ascertain a list of improvements, to limit and focus the efforts. This approach translates to best project efficiency, short time-to-market and low technical risks. At the end of this project, the required improvements will have been attained, and the corresponding new and improved gyro specification arrived at. It will positively have been proven that the SFWA specification is met with these improvements and production can start immediately.


Patent
SensoNor AS | Date: 2011-04-15

A micro-electromechanical system (MEMS) structure for an angular rate sensor, the structure being positioned between first and second silicon-insulator composite wafers formed of a plurality of structured silicon parts, electrically isolated from each other by an insulator material, the structure comprising: a mono-crystalline silicon substrate structured to form a sensing system and a frame, the sensing system being completely de-coupled from and surrounded by the frame, which is positioned between engaging surfaces of the first and second composite wafers such that the sensing system is hermetically sealed within a cavity defined by the first and second composite wafers and the frame, the sensing system including: two seismic masses having front and back surfaces; two driving beams, each having a first end attached to a seismic mass and a second end attached to the first and second composite wafers by means of fixed pedestals provided on the silicon substrate; and a bending spring arranged to directly connect between, and synchronise a primary motion of, the two seismic masses, each of the seismic masses being arranged to have a first degree of rotational freedom about an axis that is substantially perpendicular to the plane of the silicon substrate, and the seismic masses and driving beams being arranged to have a second degree of rotational freedom about an axis substantially coincident with the longitudinal axis of the driving beams; means for generating and detecting the primary motion consisting of a primary oscillation of the two seismic masses, in opposing phases, in the first degree of rotational freedom; and means of detecting a secondary motion consisting of a secondary oscillation of the two seismic masses, in opposing phases, in the second degree of rotational freedom, the means of generating and detecting the primary motion and the means of detecting a secondary motion being provided on both the front and back surfaces of each of the first and second seismic masses, wherein the sensing system is arranged such that, when the device is subjected to an angular velocity around a third axis that is substantially in the plane of the silicon substrate and perpendicular to the longitudinal axis of the beams, a Coriolis force arises which causes the secondary oscillation of the seismic masses.


Patent
Sensonor As | Date: 2011-04-15

A method for providing hermetic sealing within a silicon-insulator composite wafer for manufacturing a hermetically sealed structure, comprising the steps of: patterning a first silicon wafer to have one or more recesses that extend at least partially through the first silicon wafer; filling said recesses with an insulator material able to be anodically bonded to silicon to form a first composite wafer having a plurality of silicon-insulator interfaces and a first contacting surface consisting of insulator material; and using an anodic bonding technique on the first contacting surface and an opposing second contacting surface to create hermetic sealing between the silicon-insulator interfaces, wherein the second contacting surface consists of silicon.

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