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A method for fabricating a flip chip light emitting diode (FCLED) die includes forming an epitaxial stack on a carrier substrate having an n-type confinement layer, a multiple quantum well (MQW) layer, and a p-type confinement layer, forming a mirror layer on the p-type confinement layer, forming an n-trench in the n-type confinement layer, forming an n-conductor layer in the n-trench on the n-type confinement layer, forming a p-metal layer on the p-type confinement layer, forming a first electrical isolator layer on the n-conductor layer and a second electrical isolator layer on the p-metal layer, forming a p-pad on the first electrical isolator layer, and forming an n-pad the second electrical isolator layer.


Patent
SemiLEDs | Date: 2014-03-05

The present invention provides a light emitting diode (2), which comprises a first LED die (20a) and a second LED die (20b), each die comprising a first semi-conductive layer (200), a second semi-conductive layer (202), and a multiple quantum well layer (201) disposed between the first (200) and the second (202) semi-conductive layers, wherein the first semi-conductive layer (200) of the first LED die (20a) is coupled to the second semi-conductive layer (202) of the second LED die (20b) so as to form a serially connected structure whereby the consuming current and heat generation of the light emitting diode (2) are lowered so that the size of heat dissipating device for the light emitting diode (2) can be reduced and illumination of the light emitting diode can be enhanced.


Patent
SemiLEDs and VisEra Technologies Company Ltd | Date: 2014-03-13

The invention provides a light emitting semiconductor structure, which includes a substrate; a first LED chip formed on the substrate; an adhesion layer formed on the first LED chip; and a second light emitting diode chip formed on the adhesion layer, wherein the second LED chip has a first conductive wire which is electrically connected to the substrate.


A light emitting diode (LED) die includes a first-type semiconductor layer, a multiple quantum well (MQW) layer in electrical contact with the first-type semiconductor layer configured to emit electromagnetic radiation, and a second-type semiconductor layer in electrical contact with the multiple quantum well (MQW) layer. The light emitting diode (LED) die also includes a first pad in electrical contact with the first-type semiconductor layer via, and a second pad in electrical contact with the second type semiconductor layer. The light emitting diode (LED) die also includes a strap layer having conductive straps and contact areas located in trenches in the second type semiconductor layer.


A method for fabricating a vertical light-emitting diode (VLED) structure includes the steps of providing a carrier substrate, and forming a semiconductor structure on the carrier substrate having a p-type confinement layer, a multiple quantum well (MQW) layer in electrical contact with the p-type confinement layer configured to emit electromagnetic radiation, and an n-type confinement layer in electrical contact with the multiple quantum well (MQW) layer. The method also includes the steps of removing the carrier substrate using a laser pulse to expose an inverted surface of the n-type confinement layer, and forming a metal contact on the surface of the n-type confinement layer.


A method for fabricating a light emitting diode die includes the steps of providing a carrier substrate and forming an epitaxial structure on the carrier substrate including a first type semiconductor layer, a multiple quantum well (MQW) layer on the first type semiconductor layer configured to emit light, and a second type semiconductor layer on the multiple quantum well (MQW) layer. The method also includes the steps of forming a plurality of trenches through the epitaxial structure, forming a reflector layer on the second type semiconductor layer, forming a seed layer on the reflector layer and in the trenches, and forming a substrate on the seed layer having an area configured to protect the epitaxial structure.


Patent
SemiLEDs | Date: 2014-03-12

The present invention provides a light emitting diode (2), which comprises a first LED die (20a), a second LED die (20b), and a dummy LED die (20c), wherein the second LED die (20b) is disposed between the first LED die (20a)and the dummy LED die (20c), and each die comprises a first semi-conductive layer (200), a second semi-conductive layer (202), and a multiple quantum well layer (201) disposed between the first (200) and the second (202) semi-conductive layers. The first semi-conductive layer (200) of the first LED (20a) die is coupled to the second semi-conductive layer (202) of the second LED die (20b), and the first semi-conductive layer (200) of the second LED die (20b) is coupled to the first (200) and second (202) semi-conductive layers of the dummy LED die (20c).


A white flip chip light emitting diode (FC LED) includes a flip chip (LED) die configured to emit electromagnetic radiation; reflective sidewalls on the (LED) die; and a wavelength conversion member having a uniform thickness and a surface area greater than or equal to a footprint of the flip chip (LED) die configured to change a wavelength of the electromagnetic radiation to produce white light. A method for fabricating the white flip chip light emitting diode (FC LED) includes the steps of: providing the flip chip (LED) die; forming reflective sidewalls on the flip chip (LED) die; and forming a wavelength conversion member on the flip chip (LED) die.


A light emitting diode (LED) package includes a main VLED die; a short circuit VLED die; a lens support dam; a transparent lens attached to the lens support dam; a first electrode in electrical communication with a first semiconductor layer of the main VLED die and a second electrode in electrical communication with a second semiconductor layer of the main VLED die.


A method for fabricating a light emitting diode (LED) die includes the steps of forming an epitaxial stack on a substrate having an n-type semiconductor layer, multiple quantum well (MQW) layers, and a p-type semiconductor layer. The method also includes the steps of forming a plurality of trenches in the n-type semiconductor layer, and forming a strap layer having conductive straps and contact areas in the trenches, forming an electrical insulator layer on the strap layer, forming an n-pad on the n-type semiconductor layer, and forming a p-pad on the p-type semiconductor layer.

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