Semiconductor Research Corporation SRC

United States

Semiconductor Research Corporation SRC

United States
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Joyner W.,Semiconductor Research Corporation SRC | Kawa J.,Synopsys Inc. | Liebmann L.,IBM | Pan D.Z.,University of Texas at Austin | And 2 more authors.
IEEE Design and Test | Year: 2014

More and more techniques are being used to go down the Moore's law curve to smaller dimensions while being stuck at the same 193-nm wavelength light source, and multiple patterning methods are chief among them. This roundtable discusses the move from double patterning to triple patterning and beyond. What is the status of triple patterning today, and what does it really solve? At what dimension will it show its benefit? Will quadruple patterning be next, and when? How does multiple patterning fit in with a roadmap that includes extreme ultraviolet (EUV), direct write, and directed self-assembly? The panelists discuss the state of the art and future challenges. © 2013 IEEE.


Salmani-Jelodar M.,Purdue University | Kim S.,Intel Corporation | Ng K.,Semiconductor Research Corporation SRC | Klimeck G.,Purdue University
Applied Physics Letters | Year: 2014

In this letter, a full band atomistic quantum transport tool is used to predict the performance of double gate metal-oxide-semiconductor field-effect transistors (MOSFETs) over the next 15years for International Technology Roadmap for Semiconductors (ITRS). As MOSFET channel lengths scale below 20nm, the number of atoms in the device cross-sections becomes finite. At this scale, quantum mechanical effects play an important role in determining the device characteristics. These quantum effects can be captured with the quantum transport tool. Critical results show the ON-current degradation as a result of geometry scaling, which is in contrast to previous ITRS compact model calculations. Geometric scaling has significant effects on the ON-current by increasing source-to-drain (S/D) tunneling and altering the electronic band structure. By shortening the device gate length from 20nm to 5.1nm, the ratio of S/D tunneling current to the overall subthreshold OFF-current increases from 18% to 98%. Despite this ON-current degradation by scaling, the intrinsic device speed is projected to increase at a rate of at least 8% per year as a result of the reduction of the quantum capacitance. © 2014 AIP Publishing LLC.


Salmani Jelodar M.,Purdue University | Ilatikhameneh H.,Purdue University | Sarangapani P.,Purdue University | Mehrotra S.R.,Purdue University | And 3 more authors.
IEEE-NANO 2015 - 15th International Conference on Nanotechnology | Year: 2015

As transistors scale below 10 nm, the numbers of atoms and electrons are countable in the critical device areas. At this scale, quantum mechanical phenomena start playing an important role in the performance of the transistors. One of the major quantum mechanical effects is tunneling; i.e. tunneling between the gate and channel due to the reduction of physical oxide layer thickness and direct tunneling between the source and drain due to scaling down of channel length. This paper discusses these tunneling issues on performance of ultra-scaled transistors based on rigorous atomistic simulations and provides some solutions for scaling based on a quantitative analysis. © 2015 IEEE.

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