Shanghai, China

Semiconductor Manufacturing International Corporation is a semiconductor foundry company headquartered in Shanghai, China. It provides integrated circuit manufacturing services on 350 nm to 40 nm process technologies. SMIC has wafer fabrication sites throughout mainland China, offices in the United States, Italy, Japan, and Taiwan, and a representative office in Hong Kong. Notable customers include Qualcomm, Broadcom, and Texas Instruments. Wikipedia.


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Patent
Semiconductor Manufacturing International | Date: 2017-05-03

In some embodiments, a contact via and a fabricating method thereof are provided. The method can comprise: providing a substrate; forming a buffer layer (12) in the substrate; forming a dielectric layer (13) covering the substrate and the buffer layer; forming a through hole (14) in the dielectric layer, wherein a bottom of the through hole exposes a surface of the buffer layer; performing a roughening treatment to the exposed surface of the buffer layer to increase a roughness of the exposed surface of the buffer layer; forming a barrier layer in the through hole, and reducing a thickness of a portion of the barrier layer at the bottom of the through hole; and filling a conductive material into the through hole to form a contact via.


Patent
Semiconductor Manufacturing International | Date: 2017-05-10

A method for fabricating a semiconductor structure includes providing a substrate including a core region (II) and a peripheral region (I), forming a plurality of first fin structures in the peripheral region and a plurality of second fin structures in the core region, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure, and forming a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure and then forming a first gate oxide layer (470) on the exposed portion of each first fin structure, and removing each second dummy gate structure. Finally, the method includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.


Patent
Semiconductor Manufacturing International | Date: 2017-01-12

The present disclosure provides a thermal treatment chamber. The thermal treatment chamber includes a wafer holder to hold a to-be-processed wafer; a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of the wafer holder based on the to-be-processed wafer; and a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir to adjust the temperature of the wafer holder.


Patent
Semiconductor Manufacturing International | Date: 2017-01-23

A semiconductor device includes a semiconductor substrate, and a P-well and an N-type drift region disposed in the semiconductor substrate. The P-well includes a lower well region and an upper well region disposed above the lower well region. The lower well region includes a first surface that is near the N-type drift region, and the upper well region includes a second surface that is near the N-type drift region. A distance from the first surface of the lower well region to the N-type drift region is greater than a distance from the second surface of the upper well region to the N-type drift region.


Patent
Semiconductor Manufacturing International | Date: 2017-05-10

A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a peripheral region (I) of a substrate and a plurality of second fin structures in a core region (II) of the substrate, forming a first dummy gate structure including a first dummy oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second dummy oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate structure together with each second dummy gate electrode layer, forming a first gate oxide layer (470) on the exposed portion of each first fin structure, and then removing each second dummy gate oxide layer. The method further includes forming a first gate structure on each first fin structure and a second gate structure on each second fin structure.


Patent
Semiconductor Manufacturing International | Date: 2017-05-10

In some embodiments, a semiconductor device and a fabricating method thereof are provided. The method can comprise: providing a semiconductor substrate; forming a gate structure on the semiconductor substrate; forming an epitaxial substrate layer on the semiconductor substrate on both sides of the gate structure; forming a hard mask layer conformally covering the epitaxial substrate layer, the gate structure and the semiconductor substrate; etching the hard mask layer to form a hard mask sidewall layer on sidewall surfaces of the gate structure and on the epitaxial substrate layer; using the hard mask sidewall layer as a mask to etch the epitaxial substrate layer and the semiconductor substrate to form trenches on both sides of the gate structure; and forming a stress layer in the trenches.


Patent
Semiconductor Manufacturing International | Date: 2016-12-19

A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench.


Patent
Semiconductor Manufacturing International | Date: 2016-11-25

The present disclosure provides memory control methods and memory control apparatus. An exemplary method includes providing a memory having a targeted memory zone, the targeted memory zone having a plurality of memory cells, and a storage capacity of each memory cell being one page; receiving and reading out to-be-stored data and obtaining the targeted address information of the to-be-stored data; reading out data status of all memory cells of a targeted memory zone; determining the data status of the memory cells of the targeted memory zone; performing a programming operation to a memory cell with an erased state to write the to-be-stored data into the memory cell with the erased state; and performing an erasing operation to a memory cell having a logic address of written data to remove the logic address.


Patent
Semiconductor Manufacturing International | Date: 2017-05-24

In some embodiments, an interconnection structure, an exposure alignment system, and a fabricating method thereof are provided. The method comprises: providing a wafer, forming a first to-be-connected member and multiple first alignment members in a first conductive layer; form a first opening and multiple second alignment members in a first mask layer, the first opening is used to define a position of a second to-be-connected member; based on reference and measurement coordinates of the first alignment members, and reference coordinates and measurement coordinates of the second alignment members, obtaining wafer coordinates for characterizing a position deviation of the wafer; obtaining adjustment compensation values according to stacking offsets of a preceding wafer; adjusting a position of the wafer; forming the interconnection structure in a first dielectric layer and a second dielectric layer to electrically interconnect the first to-be-connected member and the second to-be-connected member.


Patent
Semiconductor Manufacturing International | Date: 2017-05-31

The present invention provides memory control methods and memory control apparatus. An exemplary method includes providing a memory having at least a first memory cell, an initial status of the first memory cell being at an erase state; receiving and reading out a to-be stored data to obtain a targeted address of the to-be-stored data; reading out data in each of the plurality of memory cells; determining if a data status of a memory cell corresponding to the targeted address is at a valid state according to the targeted address; performing a programming operation to the first memory cell to write the to-be-stored data into the first memory cell when the data status of the memory cell corresponding to the targeted address is at the valid state; and performing an erase operation to the memory cell corresponding to the targeted address to prepare a next data write operation.

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