Semiconductor Manufacturing International

www.smics.com/eng/index.php
Shanghai, China

Semiconductor Manufacturing International Corporation is a semiconductor foundry company headquartered in Shanghai, China. It provides integrated circuit manufacturing services on 350 nm to 40 nm process technologies. SMIC has wafer fabrication sites throughout mainland China, offices in the United States, Italy, Japan, and Taiwan, and a representative office in Hong Kong. Notable customers include Qualcomm, Broadcom, and Texas Instruments. Wikipedia.

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Patent
Semiconductor Manufacturing International | Date: 2016-12-19

A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench.


Patent
Semiconductor Manufacturing International | Date: 2017-04-05

The present disclosure provides conductive plug structures and fabrication methods thereof. An exemplary fabrication process of the conductive plug structure includes providing a substrate; forming a mask layer having an opening on a surface of the substrate; etching the substrate to form a contact hole using the mask layer as an etching mask; etching the mask layer to increase a feature size of the opening; forming an insulation layer on an inner surface of the opening, an inner surface of the enlarged opening and a surface of the mask layer to have more edge corners, a thickness of the insulation layer being greater than a thickness of the remaining mask layer; forming a conductive layer filling the contact hole on the insulation layer; and planarizing the conductive layer and the insulation layer until a surface of the mask layer is exposed.


Patent
Semiconductor Manufacturing International | Date: 2017-03-29

A phase-locked loop device may include the following elements: a phase frequency detector configured to generate a control signal; a charge pump connected to the phase frequency detector; a loop filter connected to the charge pump and configured to generate a control voltage based on a first current received from the charge pump, wherein the charge pump is configured to generate a second current based on the control signal and a first copy of the control voltage and to provide the second current to the loop filter, the second current being linearly related to the control voltage; a voltage-controlled oscillator connected to the loop filter and configured to generate an output signal based on a second copy of the control voltage, wherein a frequency of the output signal is directly proportional to the control voltage; and a signal processor connected between the voltage-controlled oscillator and the phase frequency detector.


Patent
Semiconductor Manufacturing International | Date: 2017-03-29

The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal block made of a second metal material. The plurality of first metal blocks are configured to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time.


Patent
Semiconductor Manufacturing International | Date: 2017-03-29

A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor structure that comprises a substrate and a first fin member, wherein the first fin member is connected to the substrate and comprises a first semiconductor portion; providing a first-type dopant member that directly contacts the first semiconductor portion, comprises first-type dopants, and is at least one of liquid and amorphous; and performing heat treatment on at least one of the first-type dopant member and the first semiconductor portion to enable a first portion of the first-type dopants to diffuse through a first side of the first-type dopant member into the first semiconductor portion.


Patent
Semiconductor Manufacturing International | Date: 2017-03-29

The present disclosure provides test structures, fabrication methods thereof and test methods thereof. An exemplary test structure includes a substrate having a to-be-tested region having at least one fin and a peripheral region having at least one fin surrounding the to-be-tested region; an insulation layer covering portions of side surfaces of the fins; at least one first gate structure covering side and top surfaces of the fin in the to-be-tested region; second gate structures covering side and top surfaces of the fins in the peripheral region; source/drain regions formed in portions of the fins between adjacent second gate structures and portions of the fins between the first gate structure and adjacent second gate structures; and a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region. The plurality of first conductive structures cross over and are on source/drain regions of at least two fins.


Patent
Semiconductor Manufacturing International | Date: 2017-04-12

The present disclosure provides a method for forming a transistor, including: forming a base structure, containing a first gate structure, an active layer covering the first gate structure, and an insulating structure in the active layer; forming a second gate structure on the active layer; forming a source-drain region, including a source region and a drain region in the active layer each on a different side of the second gate structure; and forming a first interlayer dielectric layer covering the base structure and the second gate structure. The method also includes:forming a first contact hole that exposes the first gate structure by etching the first interlayer dielectric layer and the insulating structure; and forming a second contact hole that exposes the second gate structure and a third contact hole that exposes the drain region by etching the first interlayer dielectric layer.


Patent
Semiconductor Manufacturing International | Date: 2017-04-12

A power-on-reset circuit (30) includes an execution circuit (201) and a control circuit (202). The execution circuit includes a first input terminal (211) connected to a power supply (Vdd not shown), a second input terminal (212) and the first output terminal (221) each initially are at a low level (low= 0). The first output terminal (221) transitions from the low level to a high level (low to high: 0 -> 1) when the first input terminal and the second input terminal have a voltage not less than a predetermined voltage (211, 212 at high=1). The control circuit (202) includes a third input terminal (231) connected to the first output terminal (221), a fourth input terminal (232) connected to the first input terminal (211), and a second output terminal (241) connected to the second input terminal (212). The second input terminal (212) transitions from the low level to the high level when a difference between the voltage at the first input terminal (211) and the voltage at the first output terminal (221) is greater than the predetermined voltage.


Patent
Semiconductor Manufacturing International | Date: 2017-04-05

The present disclosure provides a resistive random access memory (RRAM), comprising a barrier layer configured to prevent atoms in the top electrode from diffusing into the underlying resistance switching layer, and fabrication methods thereof. Preferably, an amorphous silicon resistance switching layer (320) is treated by a nitrogen plasma before forming a silicon oxide or silicon nitride barrier layer (330) and a top electrode (340) comprising aluminium (341).


Patent
Semiconductor Manufacturing International | Date: 2017-04-12

The present disclosure provides a method for forming an electrostatic discharge (ESD) protection device, including: providing a substrate including an input region; forming a plurality of fins on the substrate in the input region; forming a well region, doped with first-type ions, in the plurality of fins and in the substrate; and forming an epitaxial layer on each fin in the input region. The method further includes: forming a drain region, doped with second-type ions, in a top portion of each fin and in the epitaxial layer; forming an extended drain region, doped with the second-type ions, in a bottom portion of each fin to connect to the drain region and in a portion of the substrate, in the input region; and forming a counter-doped region, doped with the first-type ions, in a portion of the substrate between two adjacent fins to insulate adjacent extended drain regions.

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