Shanghai, China

Semiconductor Manufacturing International Corporation is a semiconductor foundry company headquartered in Shanghai, China. It provides integrated circuit manufacturing services on 350 nm to 40 nm process technologies. SMIC has wafer fabrication sites throughout mainland China, offices in the United States, Italy, Japan, and Taiwan, and a representative office in Hong Kong. Notable customers include Qualcomm, Broadcom, and Texas Instruments. Wikipedia.


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Patent
Semiconductor Manufacturing International | Date: 2016-10-18

The present disclosure provides a method for forming micro-electro-mechanical-system (MEMS) devices. The method includes providing a plurality of wafers; bonding a front surface of at least a first wafer onto a front surface of a second wafer; trimming an edge of and thinning the at least first wafer after the at least first wafer is bonded onto the second wafer; and bonding a first supporting plate onto a front surface of a third wafer. The method further includes thinning a back surface of the third wafer and forming alignment marks on a thinned back surface of the third wafer; bonding a second supporting plate onto the thinned back surface of the third wafer according to the alignment marks; and removing the first supporting plate and bonding the at least first wafer onto the third wafer according to the alignment marks to form a stack structure.


Patent
Semiconductor Manufacturing International | Date: 2016-12-07

A patterning apparatus is provided. The patterning apparatus includes a plurality of liquid jet units arranged in one or more groups and configured to jet an anti-etching liquid onto a surface of a substrate. The patterning apparatus also includes a plurality of exposure units configured to expose light on the anti-etching liquid jetted on the surface of the substrate to heat and cure the jetted anti-etching liquid to form anti-etching patterns on the surface of the substrate. Further, the patterning apparatus includes a control unit configured to control motion status and jetting status of the plurality of liquid jet units and motion status and exposure status of the plurality of exposure units, so as to form the anti-etching patterns at a predetermined line width and thickness.


Patent
Semiconductor Manufacturing International | Date: 2016-12-05

An edge bead removal apparatus is provided. The edge bead removal apparatus includes a clamping unit configured to clamp a cylindrical reticle and cause the cylindrical reticle to incline with a pre-determined angle and to rotate around a central axis. The edge bead removal apparatus also includes an edge bead removal solvent nozzle configured to spray an edge bead removal solvent to remove edge beads on both edges of the cylindrical reticle.


Patent
Semiconductor Manufacturing International | Date: 2016-11-01

A semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high.


Patent
Semiconductor Manufacturing International | Date: 2016-11-07

An integrated circuit includes a first semiconductor substrate having a first surface and a second surface opposite to the first surface, at least one first trench extending into the first semiconductor substrate from the first surface and having a first depth, at least one second trench extending into the first semiconductor substrate from the first surface and having a second depth greater than the first depth, a thinned semiconductor region with a first recessed region extending in the first semiconductor substrate from the second surface and having a first thickness, a second recessed region in the first semiconductor substrate extending from the second surface to the first surface, and a bulk dielectric layer covering the second surface of the first semiconductor substrate.


Patent
Semiconductor Manufacturing International | Date: 2017-03-29

The present disclosure provides test structures, fabrication methods thereof and test methods thereof. An exemplary test structure includes a substrate having a to-be-tested region having at least one fin and a peripheral region having at least one fin surrounding the to-be-tested region; an insulation layer covering portions of side surfaces of the fins; at least one first gate structure covering side and top surfaces of the fin in the to-be-tested region; second gate structures covering side and top surfaces of the fins in the peripheral region; source/drain regions formed in portions of the fins between adjacent second gate structures and portions of the fins between the first gate structure and adjacent second gate structures; and a plurality of first conductive structures formed between adjacent second gate structures in the peripheral region. The plurality of first conductive structures cross over and are on source/drain regions of at least two fins.


Patent
Semiconductor Manufacturing International | Date: 2017-03-29

A method for manufacturing a semiconductor device may include the following steps: preparing a semiconductor structure that comprises a substrate and a first fin member, wherein the first fin member is connected to the substrate and comprises a first semiconductor portion; providing a first-type dopant member that directly contacts the first semiconductor portion, comprises first-type dopants, and is at least one of liquid and amorphous; and performing heat treatment on at least one of the first-type dopant member and the first semiconductor portion to enable a first portion of the first-type dopants to diffuse through a first side of the first-type dopant member into the first semiconductor portion.


Patent
Semiconductor Manufacturing International | Date: 2017-03-29

The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal block made of a second metal material. The plurality of first metal blocks are configured to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time.


Patent
Semiconductor Manufacturing International | Date: 2017-03-29

A phase-locked loop device may include the following elements: a phase frequency detector configured to generate a control signal; a charge pump connected to the phase frequency detector; a loop filter connected to the charge pump and configured to generate a control voltage based on a first current received from the charge pump, wherein the charge pump is configured to generate a second current based on the control signal and a first copy of the control voltage and to provide the second current to the loop filter, the second current being linearly related to the control voltage; a voltage-controlled oscillator connected to the loop filter and configured to generate an output signal based on a second copy of the control voltage, wherein a frequency of the output signal is directly proportional to the control voltage; and a signal processor connected between the voltage-controlled oscillator and the phase frequency detector.


Patent
Semiconductor Manufacturing International | Date: 2017-04-05

The present disclosure provides conductive plug structures and fabrication methods thereof. An exemplary fabrication process of the conductive plug structure includes providing a substrate; forming a mask layer having an opening on a surface of the substrate; etching the substrate to form a contact hole using the mask layer as an etching mask; etching the mask layer to increase a feature size of the opening; forming an insulation layer on an inner surface of the opening, an inner surface of the enlarged opening and a surface of the mask layer to have more edge corners, a thickness of the insulation layer being greater than a thickness of the remaining mask layer; forming a conductive layer filling the contact hole on the insulation layer; and planarizing the conductive layer and the insulation layer until a surface of the mask layer is exposed.

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