Semiconductor Manufacturing International Corporation is a semiconductor foundry company headquartered in Shanghai, China. It provides integrated circuit manufacturing services on 350 nm to 40 nm process technologies. SMIC has wafer fabrication sites throughout mainland China, offices in the United States, Italy, Japan, and Taiwan, and a representative office in Hong Kong. Notable customers include Qualcomm, Broadcom, and Texas Instruments. Wikipedia.
Semiconductor Manufacturing International | Date: 2015-01-28
Various embodiments provide transistor devices and fabrication methods. An exemplary transistor device with improved carrier mobility can be formed by first forming a confining layer on a semiconductor substrate to confine impurity ions diffused from the semiconductor substrate to the confining layer. An epitaxial silicon layer can be formed on the confining layer, followed by forming a gate structure on the epitaxial silicon layer. A portion of the epitaxial silicon layer can be used as an intrinsic channel region. A source region and a drain region can be formed in portions of each of the epitaxial silicon layer, the confining layer, and the semiconductor substrate.
Semiconductor Manufacturing International | Date: 2015-09-24
A method for manufacturing a semiconductor device may include the following steps: preparing a substrate; providing a gate material layer that overlaps the substrate; providing a blocking layer that partially covers the gate material layer; removing a portion of the gate material layer that is not covered by the blocking layer for forming a gate electrode; providing a blocking material layer that covers both the blocking layer and the substrate; removing a portion of the blocking material layer for forming a blocking member that has an opening, wherein the opening partially exposes the blocking layer and partially exposes the substrate; and performing ion implantation through the opening to form a doped well region in the substrate.
Semiconductor Manufacturing International | Date: 2015-01-14
A method of manufacturing an embedded split-gate flash memory device is provided. The method includes: performing shallow trench isolation and chemical mechanical planarization on a semiconductor substrate comprising a flash memory region and a logic region, wherein a first oxide is formed on the semiconductor substrate and a first nitride is formed on the first oxide; forming a first photoresist over the logic region, and removing the first nitride disposed in the flash memory region; removing the first photoresist, and depositing a floating gate polysilicon material over the semiconductor substrate; performing chemical mechanical planarization on the floating gate polysilicon material; forming a control gate in the flash memory region; etching the floating gate polysilicon material to form a floating gate; forming a second photoresist over the flash memory region, and removing the first oxide and the first nitride disposed in the logic region; and removing the second photoresist.
Semiconductor Manufacturing International | Date: 2015-09-04
A method for forming a semiconductor device includes forming a conductive structure of a silicon material on a substrate and forming a planarized dielectric layer adjacent the conductive structure. The method also includes removing a portion of the dielectric layer to expose a top portion of the conductive structure and removing an outer portion of the exposed top portion of the conductive structure such that the top portion of the gate structure has a narrower width than the unexposed portion. The method further includes forming a metal layer over the exposed portion of the gate structure and a top surface of the dielectric layer, and forming a silicide layer over the top portion of the conductive structure. The width of the silicided top portion of the conductive structure is substantially the same as the width of the bottom portion of the conductive structure.
Semiconductor Manufacturing International | Date: 2015-06-08
An electronic circuit includes a clock control unit having a first input for receiving a first clock signal, a second input for receiving a second clock signal, a first clock output, and a second clock output, a first flip-flop having a first data input, a first clock input connected to the first clock output, and a first output, and a second flip-flop having a second data input, a second clock input connected to the second clock output, and a second data input connected to the first output of the first flip-flop. The clock control unit provides the first clock signal to the first clock input of the first flip-flop through the first clock output and the second clock signal to the clock input of the second flip-flop through the second clock output terminal in a sequential order.