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Semiconductor Energy Laboratory. Ltd. | Date: 2012-03-14

A lithium ion secondary battery includes a positive electrode, a negative electrode, and an electrolyte provided between the positive electrode and the negative electrode. The positive electrode includes a positive electrode current collector and a positive electrode active material layer over the positive electrode current collector. The positive electrode active material layer includes a plurality of lithium-containing composite oxides each of which is expressed by LiMPO

Semiconductor Energy Laboratory. Ltd. | Date: 2013-04-17

To provide a power feeding system and the like with which charging can be performed without a decrease in the power supply efficiency. To provide a power feeding system and the like with which can offer a power feeding service which is efficient to both a power feeding user and a power feeding provider. The power transmission state in each of power transmitting portions is monitored, the power transmitting portion having the highest power transmission efficiency is selected based on positional advantage, and the power transmitting resonance coil included in the selected power transmitting portion is kept at a first resonance frequency, whereby power transmission continues. The resonance frequency of the power transmitting resonance coil included in the non-selected power transmitting portion (the number of the non-selected power transmitting portions may be plural) is set to a second resonance frequency, whereby power transmission is stopped.

Semiconductor Energy Laboratory. Ltd. | Date: 2015-04-30

A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

Okamoto Y.,Semiconductor Energy Laboratory Company | Nakagawa T.,Semiconductor Energy Laboratory Company | Aoki T.,Semiconductor Energy Laboratory Company | Ikeda M.,Semiconductor Energy Laboratory Company | And 10 more authors.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A boosting pass gate (BPG) suitable for a programmable routing switch including a c-axis aligned crystal In-Ga-Zn-O (CAAC-IGZO) field effect transistor (FET) is proposed. The CAAC-IGZO is one of crystalline oxide semiconductors (OS). The proposed BPG (OS-based BPG, OS BPG) has a combination of a pass gate (PG) and a configuration memory (CM) cell utilizing a CAAC-IGZO FET with extremely low OFF-state current and a storage capacitor. This OS BPG achieves a routing switch with fewer transistors than a conventional routing switch having a combination of a PG and an static RAM (SRAM) cell. Owing to the boosting effect, the switching characteristics, at not only positive transition but also negative transition of input signals, of the OS BPG are improved without using overdriving. In circuits fabricated with a hybrid process of a CMOSFET and a CAAC-IGZO FET with gate lengths of 0.5 and 1.0 μm, the net delays of the OS BPG, 75 and 58 ns, at driving voltages of 2.0 and 2.5 V have been found to be less than those of the conventional routing switch (SRAM-based PG, SRAM PG) by about 79% and 62%, respectively. It has also been confirmed that a field-programmable gate array (FPGA) chip utilizing the OS BPG as a routing switch reduces the layout areas of routing switches and the whole chip by 61% and 22%, respectively, and increases the maximum operating frequencies at driving voltage of 2.0 and 2.5 V by about 2.8 times and 1.6 times of those of the FPGA chip utilizing the SRAM PG as a routing switch. © 1993-2012 IEEE. Source

Inoue H.,Semiconductor Energy Laboratory Company | Matsuzaki T.,Semiconductor Energy Laboratory Company | Nagatsuka S.,Semiconductor Energy Laboratory Company | Okazaki Y.,Semiconductor Energy Laboratory Company | And 11 more authors.
IEEE Journal of Solid-State Circuits

Emerging nonvolatile memory with an oxide-semiconductor-based thin-film transistor (TFT) using indium-gallium-zinc-oxide (IGZO) was developed. The memory is called nonvolatile oxide-semiconductor random access memory (NOSRAM). The memory cell of the NOSRAM (NOSRAM cell) consists of an IGZO TFT for data writing, a normal Si-based p-channel metal-oxide-semiconductor (PMOS) for data reading, and a cell capacitor for storing charge and controlling the PMOS gate voltage. The IGZO TFT and the cell capacitor are formed over the PMOS. Owing to extremely low-leakage-current characteristics of the IGZO TFT, the charge stored in the 2-fF cell capacitor is maintained for a long time. This long data retention realized innovative nonvolatile memory. The NOSRAM cell fabricated with the 0.8-μ m process technology demonstrated an on/off ratio of 10 7 and an endurance over 10 12 write cycles. In addition, NOSRAM with a memory capacity of 1 Mb was fabricated; the cell size was 12.32 μm 2 and the cell array size was 13.5 mm 2. The 1-Mb NOSRAM achieved basic operation at 4.5 V or less, write operation at 150 ns/page, read distribution of data "1" with 3σ= 0.10 V, and a data retention over 60 days at 85°C. © 2012 IEEE. Source

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