Semiconductor Energy Laboratory Co.

Atsugi, Japan

Semiconductor Energy Laboratory Co.

Atsugi, Japan
SEARCH FILTERS
Time filter
Source Type

A light-emitting element which uses a plurality of kinds of light-emitting dopants emitting light in a balanced manner and has high emission efficiency is provided. Further, a light-emitting device, a display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. A light-emitting element which includes a plurality of light-emitting layers including different phosphorescent materials is provided. In the light-emitting element, the light-emitting layer which includes a light-emitting material emitting light with a long wavelength includes two kinds of carrier-transport compounds having properties of transporting carriers with different polarities. Further, in the light-emitting element, the triplet excitation energy of a host material included in the light-emitting layer emitting light with a short wavelength is higher than the triplet excitation energy of at least one of the carrier-transport compounds.


Patent
Semiconductor Energy Laboratory Co. | Date: 2017-02-01

An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.


Patent
Semiconductor Energy Laboratory Co. | Date: 2017-01-27

An apparatus for forming a film having high uniformity in its film thickness distribution is provided. An evaporation source is used in which an evaporation cell, or a plurality of evaporation cells, having a longitudinal direction is formed, and by moving the evaporation source in a direction perpendicular to the longitudinal direction of the evaporation source, a thin film is deposited on a substrate. By making the evaporation source longer, the uniformity of the film thickness distribution in the longitudinal direction is increased. The evaporation source is moved, film formation is performed over the entire substrate, and therefore the uniformity of the film thickness distribution over the entire substrate can be increased.


Patent
Semiconductor Energy Laboratory Co. | Date: 2016-11-08

A signal line, a pixel connected to the signal line, a first conductive film connected to the pixel, a second conductive film including a region overlapping with the first conductive film, and a first insulating film including a region sandwiched between the first conductive film and the second conductive film and a second opening in the sandwiched region are included. The pixel includes a pixel circuit connected to the signal line, a third conductive film connected to the pixel circuit, a fourth conductive film including a region overlapping with the third conductive film, a second insulating film including a region sandwiched between the fourth conductive film and the third conductive film and an opening in the sandwiched region, a first display element electrically connected to the fourth conductive film, and a second display element connected to the pixel circuit.


Patent
Semiconductor Energy Laboratory Co. | Date: 2016-11-14

An electronic device has a structure in which two portions between which a bent portion of a display panel is positioned are each fixed to a housing. The electronic device takes two forms of a form in which the display panel is opened and a form in which the display panel is folded in three. The electronic device includes a mechanism for sliding two housings parallel to each other. The display panel is changed in shape so that a portion where a display surface of the display panel is convexly curved and a portion where the display surface of the display panel is concavely curved in the folded state move in directions parallel and opposite to each other. At this time, the two portions of the display panel which are supported by the housings are slid while their display surfaces maintain a state parallel to each other.


Patent
Semiconductor Energy Laboratory Co. | Date: 2017-01-26

A novel element is provided. A novel film formation method is provided. A novel element manufacturing method is provided. Furthermore, a film including graphene is formed at low cost and high yield. The element includes a first electrode and a second electrode located apart from the first electrode. The first electrode and the second electrode include graphene. The film including graphene is formed through a first step of forming a film including graphene oxide over a substrate, a second step of immersing the film including graphene oxide in an acidic solution, and a third step of reducing graphene oxide included in the film including graphene oxide. Furthermore, before graphene oxide included in the film including graphene oxide is reduced, the film including graphene oxide is selectively removed by a photolithography technique.


Patent
Semiconductor Energy Laboratory Co. | Date: 2017-01-27

Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.


A change in electrical characteristics is inhibited and reliability is improved in a semiconductor device using a transistor including an oxide semiconductor. One embodiment of a semiconductor device including a transistor includes a gate electrode, first and second insulating films over the gate electrode, an oxide semiconductor film over the second insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film. A third insulating film is provided over the transistor and a fourth insulating film is provided over the third insulating film. The third insulating film includes oxygen. The fourth insulating film includes nitrogen. The amount of oxygen released from the third insulating film is 110^(19)/cm^(3 )or more by thermal desorption spectroscopy, which is estimated as oxygen molecules. The amount of oxygen molecules released from the fourth insulating film is less than 110^(19)/cm^(3).


Patent
Semiconductor Energy Laboratory Co. | Date: 2017-09-27

A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; an eighth transistor; and a ninth transistor, wherein one of a source and a drain of the first transistor is directly connected to a first wiring, wherein the other of the source and the drain of the first transistor is directly connected to a second wiring, wherein one of a source and a drain of the second transistor is directly connected to a gate of the first transistor, wherein a gate of the second transistor is directly connected to a third wiring, wherein one of a source and a drain of the third transistor is directly connected to a fourth wiring, wherein the other of the source and the drain of the third transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the fourth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fourth transistor is directly connected to the gate of the first transistor, wherein a gate of the fourth transistor is directly connected to a fifth wiring, wherein one of a source and a drain of the fifth transistor is directly connected to the fourth wiring, wherein the other of the source and the drain of the fifth transistor is directly connected to a gate of the third transistor, wherein a gate of the fifth transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to a sixth wiring, wherein the other of the source and the drain of the sixth transistor is directly connected to the gate of the third transistor, wherein a gate of the sixth transistor is directly connected to the sixth wiring, wherein one of a source and a drain of the seventh transistor is directly connected to the sixth wiring, wherein the other of the source and the drain of the seventh transistor is directly connected to the gate of the third transistor. wherein one of a source and a drain of the eighth transistor is directly connected to a seventh wiring, wherein the other of the source and the drain of the eighth transistor is directly connected to the gate of the third transistor, wherein one of a source and a drain of the ninth transistor is directly connected to the seventh wiring, wherein the other of the source and the drain of the ninth transistor is directly connected to the gate of the third transistor, and wherein a gate of the ninth transistor is directly connected to the seventh wiring.


Patent
Semiconductor Energy Laboratory Co. | Date: 2017-09-13

A transistor comprising: a gate electrode layer; a gate insulating layer over the gate electrode layer; a source electrode layer and a drain electrode layer over the gate insulating layer; an oxide semiconductor layer over the gate insulating layer, which overlaps with part of the source electrode layer and the drain electrode layer; and an oxide insulating layer on and in contact with the oxide semiconductor layer, wherein the oxide semiconductor layer is expressed by InMO_(3)(ZnO)_(m) with m > 0, wherein M represents one or more metal elements selected from Ga, Al, Mn, and Co; and wherein the oxide semiconductor layer includes a superficial first region which is formed of microcrystals c-axis-oriented in a direction perpendicular to a surface of the oxide semiconductor layer, and a second region comprising microcrystals between the first region and the gate insulating layer.

Loading Semiconductor Energy Laboratory Co. collaborators
Loading Semiconductor Energy Laboratory Co. collaborators