SEMICAPS Pte Ltd.

Singapore, Singapore

SEMICAPS Pte Ltd.

Singapore, Singapore
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Goh S.H.,Globalfoundries | Yeoh B.L.,Globalfoundries | Hao H.,Globalfoundries | Chan Y.H.,Globalfoundries | And 5 more authors.
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2016

This paper proves the effects of laser pulse width on the lowering of LADA and SEU threshold laser energy. The soft failure rate is found to increase with reducing pulse widths from 100 us to 2 us. The results obtained suggest that pulsed-LADA for soft defect characterization and localization could offer notably improved SNR and turnaround time. This is because it is no longer critical to assign the test point close to the shmoo boundary which is well known to give rise to spurious signals. With a less noisy signal image, the overall debug cycle time can be shortened since multiple frames average is not required. Further driven by the motivation to seek a viable alternative to overcome the challenge of weak LADA signals due to poor transmittance of 1064 nm wavelength laser through full wafer thickness and a solid immersion lens, preliminary results based on 1122 nm wavelength laser is also presented. It is observed that though the OBIC quantum efficiency at 1122 nm is 80% lower than at 1064 nm, it is 25% higher when a solid immersion lens is used. Copyright © 2016 ASM International® All rights reserved.


Ravikumar V.K.,AMD Inc | Ravikumar V.K.,Singapore University of Technology and Design | Ranganathan G.,AMD Inc | Phoa S.L.,AMD Inc | And 5 more authors.
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2016

Time-resolved laser assisted device alteration (TR-LADA) has interesting applications to reduce the spatial spread of LADA site, as well as benefit device design debug. This paper describes an implementation using a 1063nm wavelength nanosecond pulse-on-demand laser diode to obtain a timing resolution of 1-2 tester cycles and spatial resolution enhancements to LADA sites. We also present potential capabilities of TR-LADA in the debug of analog circuitry. Copyright © 2016 ASM International® All rights reserved.


Bruce M.R.,SEMICAPS Pte Ltd. | Ross L.K.,SEMICAPS Pte Ltd. | Scholz C.,LeCroy Corporation | Joshi L.,LeCroy Corporation | And 2 more authors.
Microelectronics Reliability | Year: 2012

Laser timing probes are used to display waveforms at single points or frequencies mapped throughout a field of view in an effort to locate logic failures. By focusing just on the logic state itself, this paper describes an approach that quickly determines the logic timing patterns and uses this information to identify logic pattern mismatches on-the-fly at specific locations, such as cells in a scan chain. Various applications and case studies are presented. © 2012 Elsevier Ltd. All rights reserved.


Teo J.K.J.,National University of Singapore | Chua C.M.,SEMICAPS Pte Ltd | Koh L.S.,SEMICAPS Pte Ltd | Phang J.C.H.,National University of Singapore | Phang J.C.H.,SEMICAPS Pte Ltd
Applied Physics Letters | Year: 2011

An n-channel metal-oxide-semiconductor (NMOS) transistor has been characterized using backside laser reflectance modulation based on static and dynamic techniques. The static techniques do not have the required sensitivity. With the dynamic technique, the reflectance modulations of the channel at different operating points of the NMOS transistor are distinct, with the pinch-off clearly visible. © 2011 American Institute of Physics.


Teo J.K.J.,National University of Singapore | Chua C.M.,SEMICAPS Pte Ltd. | Koh L.S.,SEMICAPS Pte Ltd. | Phang J.C.H.,National University of Singapore | Phang J.C.H.,SEMICAPS Pte Ltd.
IEEE International Reliability Physics Symposium Proceedings | Year: 2011

The variation of backside reflectance modulation effects on metal line samples at different electrical bias and silicon backside thicknesses is investigated. Negative reflected intensity modulation is observed with temperature increase which is one to two orders of magnitude higher than published results. A backside reflectance model is developed to explain the experimental results. © 2011 IEEE.


Goh S.H.,Globalfoundries | Pan Y.,Globalfoundries | You G.F.,Globalfoundries | Chan Y.H.,Globalfoundries | And 9 more authors.
Review of Scientific Instruments | Year: 2012

Frequency mapping methodology is an effective diagnostic tool for detection of manufacturing defects in scan chains. It analyses reflected laser modulations from toggling scan cells to localize defective scan path or scan cell. In this paper, we demonstrate experimentally that the use of solid immersion lens technology to enhance signal and spatial resolution is not a prerequisite for this technique up till 28 nm technology node. We present case studies to show the effectiveness of frequency mapping for detecting systematic and random broken scan chain failures on a 28 nm technology node test chip. We achieved 81 success rate in this methodology. © 2012 American Institute of Physics.


Goh S.H.,Globalfoundries | You G.F.,Globalfoundries | Yeoh B.L.,Globalfoundries | Chan Y.H.,Globalfoundries | And 3 more authors.
Conference Proceedings from the International Symposium for Testing and Failure Analysis | Year: 2013

Wafer level tester-based fault isolation (FI) tool exists back in 2008 but is not widely adopted by industry. This is expected because such tool is commonly known for its primary role in dynamic electrical FI. Since packages are readily available, there is little motivation in using wafers. This paper provides a different perspective to consider such tool as part of a wafer level debug solution to enhance current failure pre diagnostic and diagnosis capabilities, to meet requirements for fast and effective yield ramp. Test cases are presented to support this perspective and a roadmap that guides next generation wafer level FI tool is also proposed at the end of the paper. Copyright © 2013 ASM International® All rights reserved.


Bruce M.R.,SEMICAPS Pte Ltd. | Ross L.K.,SEMICAPS Pte Ltd. | Chua C.M.,SEMICAPS Pte Ltd.
Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA | Year: 2014

On Die Logic Analysis (ODLA) uses a scanning optical microscope (SOM) to quickly determine logic timing patterns, and then uses this information to identify logic pattern matches/mismatches on-the-fly from the backside. In this paper, the ODLA system and methodology will be described along with how, in one universal method, it can replace a slew of techniques such as Laser Timing Probe (LTP), Frequency Mapping (FM), and Phase Imaging (PI). It will be demonstrated on a chain of scan cells. © 2014 IEEE.


Patent
Semicaps Pte Ltd | Date: 2014-09-26

A method and an apparatus for cooling a semiconductor device. The method comprises the steps of contacting a surface of the semiconductor device with respective end portions of an array of contact elements thermally coupled to a cooling fluid, and disposing a flexible, heat conductive sheet between the respective end portions of the contact elements and the surface of the semiconductor device for transferring heat generated in the semiconductor device to the cooling fluid via the sheet and the contact elements.


Patent
Semicaps Pte Ltd | Date: 2013-05-06

A wafer stage and a method of supporting a wafer for inspection. the wafer stage comprises a platform for supporting a wafer such that a backside of the wafer is suspended above a cavity of the platform; and a support structure disposed substantially within the cavity for supporting a portion of the wafer; wherein the wafer stage is adapted for relative movement of the platform with respect to the support structure for alignment of the wafer with respect to a probe.

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