Semi Conductor Laboratory Scl

Bhubaneshwar, India

Semi Conductor Laboratory Scl

Bhubaneshwar, India
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Lele A.,Indian Institute of Technology Bombay | Sadana S.,Indian Institute of Technology Bombay | Singh A.,Semi Conductor Laboratory SCL | Jatana H.S.,Semi Conductor Laboratory SCL | Ganguly U.,Indian Institute of Technology Bombay
Device Research Conference - Conference Digest, DRC | Year: 2017

Internet of Things (IoT) requires chip level unique identification like a random binary barcode. For secure random binary barcode, a physically un-clonable function (PUF) is preferred over software which produces a random binary barcode based on fundamentally stochastic (hence un-clonable) processes e.g. Ring Oscillator Frequency due to scaled transistor variability[1], RRAM off-state current due to stochastic nature of filaments [2], stochastic switching in MTJ [3]. As IoT applications maybe partially enabled by previous generation technology nodes e.g. 90nm or 180nm [4], such strategies are challenging e.g. RO variability is low at 180nm technology [1] while MTJ and RRAM require advanced materials integration at 180nm, which has cost-implications. Alternatively, fundamentally stochastic gate oxide breakdown based OTP / RNG has been commercialized [5-6]. However, it requires higher breakdown voltage (Vbd) than supply voltage (i.e. Vbd e.g. 3.3V at 180nm technology). This requires high voltage transistors and charge pumps. In this work, we propose the stochastic breakdown in PECVD oxide for OTP PUF to demonstrate broader Vbd distribution, lower Vgbd than 3.3 V. We compare the failure rates, voltage tolerance window for random numbers generation (RNG) using NIST tests [7] and PUF uniqueness tests [2]. © 2017 IEEE.


Balodi D.,University of Hyderabad | Saha C.,Semi Conductor Laboratory Scl
2012 International Conference on Devices, Circuits and Systems, ICDCS 2012 | Year: 2012

The importances of MOSFET parameter extraction process along with the requirements for good optimization strategy to obtain better modeling results are discussed. Scope for achieving the flexibilities in parameter extraction process and strategy formation has also been discussed with the example of BSIM MOSFET model in 0.8 μm CMOS technology and it is argued that with the poor extraction strategy, even the more powerful BSIM3 (Level-49) model produces the comparable results to that of BSIM (Level-13) model. Finally the BSIM (Level-13 and Level-49) modeling efforts for various geometry devices are shown in comparative manner which are followed by qualitative analysis to conclude the important aspects of these models with optimization effects. © 2012 IEEE.

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