Kim H.H.,SEMES |
Kim D.G.,Ajou University |
Choi J.Y.,Ajou University |
Park S.C.,Ajou University
Computers and Industrial Engineering | Year: 2017
The tire manufacturing process consists of four major steps, including mixing, component preparation, building, and curing. Among these, the mixing process is the most important, since it produces a type of synthesized rubber called a compound, which determines various features of the tire and consumes 70% of the overall manufacturing budget. However, despite the importance of mixing, there is little research on this process. Thus, in this study, we consider a scheduling problem for a tire mixing process and suggest an efficient particle swarm optimization (PSO) algorithm for minimizing makespan. Specifically, we design a system in which particle coordination and velocity are used to generate a processing sequence for compounds and machine allocation information, while being updated in successive steps. The superiority of the proposed PSO algorithm is shown with numerical experiments that compare the solutions found by the proposed algorithm with those obtained from a mixed integer linear programming model developed in previous research. © 2017 Elsevier Ltd
News Article | December 5, 2016
WiseGuyReports.Com Publish a New Market Research Report On – “3D Semiconductor Packaging Industry Global Key Vendors,Manufacturers,Suppliers and Analysis Market Report 2020”. The analysts forecast the global 3D semiconductor packaging market to grow at a CAGR of 16.27% during the period 2016-2020. Recent technology advances along with improved durability, reduced energy consumption, superior performance, enhanced quality, and highly efficient features of 3D semiconductor packaging equipment are making this equipment attractive packaging proposition in the semiconductor industry, especially in the consumer electronics industry. The increasing demand for consumer electronics is expected to increase the revenue of the global 3D semiconductor packaging market during the forecast period. For more information or any query mail at [email protected] Covered in this report The report covers the present scenario and the growth prospects of the global 3D semiconductor packaging market for 2016-2020. To calculate the market size, the report considers revenue generated from the sales of 3D semiconductor packaging equipment to semiconductor component manufacturers. The market is divided into the following segments based on geography: • Americas • APAC • EMEA The report, Global 3D Semiconductor Packaging Market 2016-2020, has been prepared based on an in-depth market analysis with inputs from industry experts. The report covers the market landscape and its growth prospects over the coming years. The report also includes a discussion of the key vendors operating in this market. Key vendors • Amkor Technology • SUSS Microtek • EV Group • Tokyo Electron Other prominent vendors • ACCRETECH Tokyo Seimitsu • Rudolph Technologies • SEMES • Ultratech • ULVAC Market driver • Need to control chip design costs • For a full, detailed list, view our report Market challenge • High capital investment in 3D semiconductor packaging • For a full, detailed list, view our report Market trend • Short replacement cycle of portable electronic devices • For a full, detailed list, view our report Key questions answered in this report • What will the market size be in 2020 and what will the growth rate be? • What are the key market trends? • What is driving this market? • What are the challenges to market growth? • Who are the key vendors in this market space? • What are the market opportunities and threats faced by the key vendors? • What are the strengths and weaknesses of the key vendors? PART 02: Scope of the report • Definition • Report overview • Base year and forecast period • Geographical segmentation • Common currency conversion rates • Vendor offerings PART 06: Market segmentation by application • Global 3D semiconductor packaging market by application 2015-2020 • Consumer electronics • Others PART 07: Geographical segmentation • 3D semiconductor packaging market in APAC • 3D semiconductor packaging market in EMEA • The Americas For more information or any query mail at [email protected] Wise Guy Reports is part of the Wise Guy Consultants Pvt. Ltd. and offers premium progressive statistical surveying, market research reports, analysis & forecast data for industries and governments around the globe. Wise Guy Reports features an exhaustive list of market research reports from hundreds of publishers worldwide. We boast a database spanning virtually every market category and an even more comprehensive collection of market research reports under these categories and sub-categories.
Jeon M.H.,Sungkyunkwan University |
Mishra A.K.,Sungkyunkwan University |
Kang S.-K.,Sungkyunkwan University |
Kim K.N.,Sungkyunkwan University |
And 4 more authors.
Current Applied Physics | Year: 2013
60 MHz pulsed radio frequency (rf) source power and 2 MHz continuous wave rf bias power, were used for SiO2 etching masked with an amorphous carbon layer (ACL) in an Ar/C4F8/O2 gas mixture, and the effects of the frequency and duty ratio of the 60 MHz pulse rf power on the SiO2 etch characteristics were investigated. With decreasing duty ratio of the 60 MHz pulse rf power, not only the etch rate of SiO2 but also the etch rate of ACL was decreased, however, the etch selectivity of SiO2 over ACL was improved with decreasing the duty ratio. On the other hand, when the pulse frequency was varied at a constant duty ratio, no significant change in the etch rate and etch selectivity of both materials could be observed. The variation of the etch characteristics was believed to be related to the change in the gas dissociation characteristics caused by the change in the average electron temperature for different pulsing conditions. The improvement in the etch selectivity with the decrease of duty ratio, therefore, was related to the decreased gas dissociation of C 4F8 by the decrease of average electron temperature and, which resulted in a change in composition of the fluorocarbon polymer on the etched materials surface from C-C rich to CF2 rich. With decreasing the duty ratio, not only the etch selectivity but also the improvement in the SiO2 etch profile could be observed. © 2013 Elsevier B.V. All rights reserved.
Lee B.-J.,Kangwon National University |
Cho S.-C.,SEMES |
Jeong G.-H.,Kangwon National University
Current Applied Physics | Year: 2015
We demonstrate the surface treatment of graphene using an atmospheric pressure plasma jet (APPJ) system. The graphene was synthesized by a thermal chemical vapor deposition with methane gas. A Mo foil and a SiO2 wafer covered by Ni films were employed to synthesize monolayer and mixed-layered graphene, respectively. The home-built APPJ system was ignited using nitrogen gas to functionalize the graphene surface, and we studied the effect of different treatment times and interdistance between the plasma jet and the graphene surface. After the APPJ treatment, the hydrophobic character of graphene surface changed to hydrophilic. We found that the change is due to the formation of functionalities such as hydroxyl and carboxyl groups. Furthermore, it is worth noting that the nitrogen plasma treatment induced charge doping on graphene, and the pyridinic nitrogen component in the X-ray photoelectron spectroscopy spectrum was significantly enhanced. We conclude that the atmospheric pressure plasma treatment enables controlling the graphene properties without introducing surface defects. © 2015 Elsevier B.V. All rights reserved.
Kim H.J.,Sungkyunkwan University |
Jeon M.H.,Sungkyunkwan University |
Mishra A.K.,Sungkyunkwan University |
Kim I.J.,SEMES |
And 2 more authors.
Japanese Journal of Applied Physics | Year: 2015
A SiO2 layer masked with an amorphous carbon layer (ACL) has been etched in an Ar/C4F8 gas mixture with dual frequency capacitively coupled plasmas under variable frequency (13.56-60MHz)/pulsed rf source power and 2MHz continuous wave (CW) rf bias power, the effects of the frequency and pulsing of the source rf power on the SiO2 etch characteristics were investigated. By pulsing the rf power, an increased SiO2 etch selectivity was observed with decreasing SiO2 etch rate. However, when the rf power frequency was increased, not only a higher SiO2 etch rate but also higher SiO2 etch selectivity was observed for both CW and pulse modes. A higher CF2/F ratio and lower electron temperature were observed for both a higher source frequency mode and a pulsed plasma mode. Therefore, when the C 1s binding states of the etched SiO2 surfaces were investigated using X-ray photoelectron spectroscopy (XPS), the increase of C-Fx bonding on the SiO2 surface was observed for a higher source frequency operation similar to a pulsed plasma condition indicating the increase of SiO2 etch selectivity over the ACL. The increase of the SiO2 etch rate with increasing etch selectivity for the higher source frequency operation appears to be related to the increase of the total plasma density with increasing CF2/F ratio in the plasma. The SiO2 etch profile was also improved not only by using the pulsed plasma but also by increasing the source frequency. © 2015 The Japan Society of Applied Physics.
News Article | November 4, 2016
— 2016 global fan-in wafer level packaging market research says one trend gaining popularity in this market is increase in wafer size. The global semiconductor industry witnessed an increase in the size of silicon wafers, from 100 mm to 300 mm, during the last four decades. The shift to larger diameter wafers reduces the cost of manufacturing semiconductor ICs by 20%-25%. At present, the industry predominantly uses 300-mm wafers to manufacture ICs. This trend is expected to maintain its momentum during the forecast period. Complete report on fan-in wafer level packaging market spread across 62 pages, analyzing 4 major companies and providing 38 data exhibits are now available at http://www.reportsnreports.com/reports/738713-global-fan-in-wafer-level-packaging-market-2016-2020.html The following companies are the key players in the global fan-in wafer level packaging market: STATS ChipPAC, STMicroelectronics, TSMC, and Texas Instruments. Other Prominent Vendors in the market are: Rudolph Technologies, SEMES, SUSS MicroTec, Ultratech, and FlipChip International. According to the fan-in wafer level packaging market report, the surging demand for compact electronic devices in sectors such as telecommunications, automotive, industrial manufacturing, and healthcare has generated the need for miniaturized semiconductor ICs. With the emergence of products such as 3D ICs and MEMS devices, the electronic equipment is becoming compact and user-friendly, which involves changes in IC designing such as finer patterning. Order a copy of Global Fan-in Wafer Level Packaging Market 2016-2020 report @ http://www.reportsnreports.com/purchase.aspx?name=738713 The analog and mixed ICs accounted for around 72% of the global fan-in wafer level packaging market in 2015 and is expected to grow at a steady rate during the forecast period. In 2015, MEMS and sensors accounted for around 9% of the global fan-in WLP market. The key revenue generators of the global MEMS market are the consumer electronics and automotive segments. Logic and memory ICs will grow at a CAGR of around 6% in the global fan-in wafer level packaging market, during the forecast period. The requirement for high-powered processors, especially for the automation purposes, has prompted the demand for fan-in WLP solutions in the logic IC segment, as they form an integral part of IC packaging at the manufacturing level. The report, Global Fan-In Wafer Level Packaging Market 2016-2020, has been prepared based on an in-depth market analysis with inputs from industry experts. This report covers the present scenario and the growth prospects of the global fan-in wafer level packaging market for 2016-2020. To calculate the market size, the report considers the revenue generated from the sales of packaged fan-in WLPs in various application segments such as analog and mixed IC, wireless connectivity, logic and memory IC, micro-electro-mechanical systems (MEMS) and sensors, and complementary metal-oxide-semiconductor (CMOS) image sensor In terms of geographical regions, APAC will be the major revenue contributor to the fan-in wafer level packaging market throughout the next four years. This is mainly due to the presence of a number of semiconductor foundries in this region. Moreover, the rise in demand for semiconductor devices due to the presence of prominent consumer electronics manufacturers, such as Samsung, Sony, LG, Toshiba, and Panasonic, will also bolster this market’s growth prospects. About Us: ReportsnReports.com is your single source for all market research needs. Our database includes 500,000+ market research reports from over 100+ leading global publishers & in-depth market research studies of over 5000 micro markets. With comprehensive information about the publishers and the industries for which they publish market research reports, we help you in your purchase decision by mapping your information needs with our huge collection of reports. For more information, please visit http://www.reportsnreports.com/reports/738713-global-fan-in-wafer-level-packaging-market-2016-2020.html
News Article | November 7, 2016
MarketStudyReport.com adds “Global Fan-in Wafer Level Packaging Market 2016-2020” new report to its research database. The report spread across 62 pages with table and figures in it. The research analysts forecast the global fan-in WLP market to grow at a CAGR of 9.63% during the period 2016-2020. About Fan-in WLP Chip-scale packaging (CSP) emerged in the 1990s. By 1998, wafer-level CSPs emerged as the most preferred form of chip packaging solutions due to their low cost benefits in applications, ranging from application-specific integrated circuits (ASICs) and microprocessors to electrically erasable programmable read-only memory (EEPROM). WLP is one of the key trending technologies used for CSP and is gaining popularity among fabless and foundry companies globally. Browse full table of contents and data tables at https://www.marketstudyreport.com/reports/global-fan-in-wafer-level-packaging-market-2016-2020/ Covered in this report The report covers the present scenario and the growth prospects of the global fan-in WLP market for 2016-2020. To calculate the market size, the report considers the revenue generated from the sales of packaged fan-in WLPs in various application segments such as analog and mixed IC, wireless connectivity, logic and memory IC, micro-electro-mechanical systems (MEMS) and sensors, and complementary metal-oxide-semiconductor (CMOS) image sensor The market is divided into the following segments based on geography: APAC North America Europe Research report, Global Fan-in WLP Market 2016-2020, has been prepared based on an in-depth market analysis with inputs from industry experts. The report covers the market landscape and its growth prospects over the coming years. The report also includes a discussion of the key vendors operating in this market. Key vendors STATS ChipPAC STMicroelectronics TSMC Texas Instruments Other prominent vendors Rudolph Technologies SEMES SUSS MicroTec Ultratech FlipChip International Market driver High demand for miniaturized electronics For a full, detailed list, view our report Market challenge Cyclical nature of semiconductor industry For a full, detailed list, view our report Market trend Increase in wafer size For a full, detailed list, view our report Key questions answered in this report What will the market size be in 2020 and what will the growth rate be? What are the key market trends? What is driving this market? What are the challenges to market growth? Who are the key vendors in this market space? What are the market opportunities and threats faced by the key vendors? What are the strengths and weaknesses of the key vendors? To receive personalized assistance, write to us @ [email protected] with the report title in the subject line along with your questions or call us at +1 866-764-2150