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Hill R.J.W.,SEMECH | Huang J.,SEMECH | Barnett J.,SEMECH | Kirsch P.,SEMECH | Jammy R.,SEMECH
Solid State Technology | Year: 2010

It is widely expected that around the 11-15nm technology node, strained silicon may run out of steam and alternative channel materials will be required to achieve the low power performance targets set out in the International Technology Roadmap for Semiconductors (ITRS) [1]. While several grand challenges must be overcome to realize III-V nMOS incorporation in future CMOSFETs, this article addresses three of the most important; improvement of high-k/III-V interface, down selection of junction technology, and co-integration for VLSI using a manufacturaba process flow on a silicon platform.

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