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Austin, TX, United States

SEMATECH is a not-for-profit consortium that performs research and development to advance chip manufacturing. SEMATECH has broad engagement with various sectors of the R&D community, including chipmakers, equipment and material suppliers, universities, research institutes, and government partners. The group is funded by member dues. Wikipedia.


Patent
Sematech | Date: 2014-10-27

The present invention includes methods directed to improved processes for producing a monolayer of sulfur or selenium on the surface of a semiconductor. As a surface layer, it functions to passivate the surface; if annealed, it provides a doping element.


An apparatus, system, and method for cleaning surfaces is presented. One embodiment of the system includes an array of surface acoustic wave (SAW) transducers coupled to a substrate. The system may include a positioning mechanism coupled to at least one of a target surface or the array of SAW transducers, and configured to position the array of SAW transducers within an effective cleaning distance of a target surface. The system may also include a cleaning liquid supply arranged to provide cleaning liquid for coupling the array of SAW transducers to the target surface. The system may further include a controller coupled to the array of SAW transducers and configured to activate the array of SAW transducers. At least one of the SAW transducers may be formed to focus cleaning liquid on a focal point and jet cleaning liquid in a direction substantially out of the place of the SAW transducer.


Patent
Sematech and Asahi Glass Co. | Date: 2014-05-08

A deposition chamber shield having a stainless steel coating of from about 100 microns to about 250 microns thick wherein the coated shield has a surface roughness of between about 300 microinches and about 800 microinches and a surface particle density of less than about 0.1 particles/mm


Patent
Sematech and New York University | Date: 2014-01-17

Methods and compositions are provided for reducing or eliminating charge buildup during scanning electron microscopy (SEM) metrology of a critical dimension (CD) in a structure produced by lithography. An under layer is utilized that comprises silicon in the construction of the structure. When the lithography structure comprising the silicon-comprising under layer is scanned for CDs using SEM, the under layer reduces or eliminates charge buildup during SEM metrological observations.


Patent
Sematech and Asahi Glass Co. | Date: 2014-05-08

A process for cleaning and restoring deposition shield surfaces which results in a cleaned shield having a surface roughness of between about 200 microinches and about 500 microinches and a particle surface density of less than about 0.1 particles/mm

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