Agency: National Aeronautics and Space Administration | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 599.30K | Year: 2011
While VPX shows promise as an open standard COTS computing and memory platform, there are several challenges that must be overcome to migrate the technology for a space application. For the Phase I SBIR, SEAKR investigated the 3u VPX architecture for the space environment for advanced memory and processing systems. The SBIR investigation focused on researching innovative switch fabric architectures, identifying and qualifying the building blocks for a space qualified VPX system, and addressed some of the challenges associated with VPX flash memory modules. The areas of innovation that have been addressed are outlined below:?Research and evaluate the basic building blocks required for a high speed switch VPX architecture?Explore advanced EDAC and innovative wear leveling techniques for commercially upscreened flash memory for space applications?Evaluate different techniques for very high speed flash memory access ratesThe Phase II SBIR will build on the Phase I study to produce a deliverable engineering model of a 3U VPX flash memory module.
SEAKR Engineering, Inc. | Date: 2012-05-01
Methods, systems, and devices for distributed computing are provided. Clusters of nodes are provided, each node have a communication link to a primary I/O switch as well as to two other nodes, thereby providing redundant alternative communication paths between different components of the system. Primary and redundant I/O switching modules may provide further redundancy for high availability and high reliability applications, such as applications that may be subjected to the environment as would be found in space, including radiation effects. Nodes in a cluster may provide data storage, processing, and/or input/output functions, as well as one or more alternate communications paths between system components. Multiple clusters of nodes may be coupled together to provide enhanced performance and/or reliability.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 710.32K | Year: 2016
The SEAKR team proposes to continue development of the advanced protocol routing system begun in the Phase I effort, to reduce risk toward a flight deployable system for SATCOM assets such as Iridium NEXT. SEAKRs development of the Iridium NEXT modem...
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 749.68K | Year: 2010
SEAKR Engineering’s Application Independent Processor (AIP) standard product integrates FPGAs, GPPs and malleable interface support into a flexible onboard processor designed to support many spacecraft applications. The AIP architecture reduces risk, costs, and schedule for satellite missions by providing a reconfigurable space-based platform and variations of the system are slated to be deployed in a variety of missions including communications waveform processing, real-time image processing in the ARTEMIS sensor on TacSat-3, and is being baselined for the vision processor unit on NASA’s Orion crew exploration vehicle. This capable system concept is well suited to processor-intensive missions like 3GIRS sensor OBP and the results of the preliminary study undertaken by SEAKR Engineering in Phase I of this SBIR have identified areas for improvement to meet the future goals of the program. The goals of phase II are to work toward upgrading the AIP to meet current and future 3GIRS requirements and thus improve the system’s commercialization success. Ultimately, the technology developed under this program will be integrated into the planned 3GIRS missions as well as other space-based sensor processing missions. BENEFIT: The 3GIRS-OBP will provide a single subsystem for payload processing, on-board memory storage, control, and power management. It is capable of hanlding several Gbit/sec of data and can process in real time.
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 678.00K | Year: 2010
The MAESTRO Phase II SBIR’s focus is the design and build of a single board processor based on the MAESTRO chip developed by the U.S. Government. The board will be on a commercial VPX (Vita-46) 6U standard. The processor chip used on the board is a multi-core processor, with 49 identical processing cores, 4 banks of DDR2 memory, and 4 XAUI 10Gb interfaces. The VPX standard supports interfaces up to 40Gbps. The processor board will be designed as a prototype software development station for use by the MAESTRO community. The development includes an initial board support package, hardware and software documentation and porting of a software application from the phase I SBIR for validation of throughput. BENEFIT: The MAESTRO board has a number of applications, both terrestrial and space based. The initial prototype board will be used as a software development station for algorithmic development. The prototype board can be used as a verification vehicle for radiation testing and characterization of the MAESTRO processor itself. The board uses a powerful multi-core processor that has been developed using rad-hard by design libraries, and can be spun into a flight version for space applications.