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Guo A.,Sichuan Institute of Solid State Circuits | Hu R.B.,Science and Technology on Analog Integrated Circuit Laboratory
Applied Mechanics and Materials | Year: 2014

A capacitor memory erasing technique for pipeline ADC is introduced, which insert a clearing phase to the traditional working timing sequence of the MDAC to erasing the residual charges on the sampling capacitor. The measurement shows that the 14-bit pipeline ADC adopting the proposed technique can achieve a sampling rate of 250MSPS with SNR 69dB, SFDR 80dB, compared with the traditional ADC of sampling rate 100MSPS, SNR 60dB, SFDR 71dB, which proves the proposed technique can improve the performances of pipeline ADCS obviously. © (2014) Trans Tech Publications, Switzerland.


Hu R.,Science and Technology on Analog Integrated Circuit Laboratory | Zhang X.,Sichuan Institute of Solid State Circuits
2015 International Conference on Optoelectronics and Microelectronics, ICOM 2015 | Year: 2015

A switch-decoded based current-steering architecture is proposed for calibration DAC of ADCs. The circuit and working principle of the proposed switch-decoded current-steering DAC is introduced. A 14-bit DAC is realized in 0.18um CMOS process by combining an 8-bit switch-decoded current-steering DAC with a 6-bit binary-weight DAC. The chip area taken by the 14-bit DAC is only 0.1 square millimeters. The simulation shows that the DNL is +0.18/-0.52LSB and the INL is +1.5/-2.3LSB. © 2015 IEEE.


Hu R.,Science and Technology on Analog Integrated Circuit Laboratory | Zhang X.,Sichuan Institute of Solid State Circuits
2015 International Conference on Optoelectronics and Microelectronics, ICOM 2015 | Year: 2015

A CMOS analog front end for ADCs is introduced, which can sample and hold the incoming analog signal for the following ADC. As a result, the ADC can deal with a signal which is unchanged at the working period of the ADC. The analog front is a full differential architecture including two completely symmetrical signal paths, which receive the normal and inverted phase parts of a full differential signal, respectively. The outputs of the two signal paths are inputted into the normal and inverted phase input terminals of a full differential amplifier. A protection is added to the circuit to speed up the sampling switch. A resistor is added to filter out the high frequency spur caused by the switching action of circuit. As a result, the proposed circuit has higher sampling rate and performances than other related sample and hold circuit. Simulation shows that the analog front consumes only 80mW power and has a SNR of 67dB as well as a SFDR of 70dB at a sampling rate of 2.4GSPS. © 2015 IEEE.


Ye R.K.,Sichuan Institute of Solid State Circuits | Hu R.B.,Science and Technology on Analog Integrated Circuit Laboratory
Advanced Materials Research | Year: 2014

A kind of CMOS bandgap reference circuit with high order temperature compensation is introduced [1]. Compared to the traditional circuit, the bandgap reference proposed here has several advantages such as better temperature stability, smaller chip area, lower power consumption, self power-on, and so on. Our design can be used in analog-to-digital or digital-to-analog converters, where high performance bandgap reference is required. © (2014) Trans Tech Publications, Switzerland.


Hu R.,Sichuan Institute of Solid State Circuits | Tang J.,Chongqing University of Posts and Telecommunications | Tang J.,Science and Technology on Analog Integrated Circuit Laboratory
2012 2nd International Conference on Consumer Electronics, Communications and Networks, CECNet 2012 - Proceedings | Year: 2012

A novel bootstrapped switch is introduced in this paper At first, the mathematics built in the bootstrapped switch is discussed Secondly, the prototype of the bootstrapped switch is described. At last, the transistor-level circuit of the bootstrapped switch is given. The performance of the bootstrapped switch is tested indirectly by stimulating a sampling and holding circuit containing the bootstrapped switch. The stimulated results show that the bootstrapped switch has a performance with SFDR more than 89dBc, and SNR bigger than 79dB. © 2012 IEEE.


Hu R.,Sichuan Institute of Solid State Circuits | Tang J.,Chongqing University of Posts and Telecommunications | Tang J.,Science and Technology on Analog Integrated Circuit Laboratory
2012 2nd International Conference on Consumer Electronics, Communications and Networks, CECNet 2012 - Proceedings | Year: 2012

A novel full differential double sampling circuit is presented in the paper. The traditional full differential single sampling circuit is compared with the proposed full differential double sampling one to show that the latter has more efficiency and higher speed The proposed full differential double sampling circuit is designed in TSMC 0.18m CMOS process technology. The simulation results show that the SFDR of the proposed full differential double sampling circuit is 81.36dB at 200MS/s. Further simulations show that the proposed full differential double sampling circuit has twice better performance than the traditional one. © 2012 IEEE.


Zhou K.,University of Electronic Science and Technology of China | Luo X.,University of Electronic Science and Technology of China | Luo X.,Science and Technology on Analog Integrated Circuit Laboratory | Xu Q.,University of Electronic Science and Technology of China | And 2 more authors.
IEEE Transactions on Electron Devices | Year: 2014

A low specific ON-resistance (RON,sp) silicon-oninsulator (SOI) p-channel LDMOS (pLDMOS) with an enhanced reduced surface field (RESURF) effect and self-shielding effect of the back-gate (BG) bias is proposed and investigated. It features an oxide trench and the p-drift region surrounding the trench, which is built on the n-SOI layer. In the OFFstate, first, the extended trench gate also acts as a gate field plate; second, the p-drift and the n-SOI layer forms a folded RESURF structure. Both increase the doping dose of the p-drift and modulate electric field (E-field) distribution; third, the oxide trench not only reduces the device pitch but also enhances the E-field strength. All of them result in a low RON,SP and a high breakdown voltage (BV) with a reduced device pitch. The free charges induced on the SOI/buried oxide (BOX) interface not only enhance the E-field strength in the BOX but also effectively shield the influence of BG bias effect in a wide range. The proposed pLDMOS achieves state-of-the-art improvement in the tradeoff between BV and R ON,SP. Compared with the p-top SOI pLDMOS, the proposed device reduces the RON,SP by 79% at the same BV. A strong immunity to the BG bias effect is demonstrated and analyzed in detail. © 2014 IEEE.


Shen X.F.,Science and Technology on Analog Integrated Circuit Laboratory | Hu R.B.,Science and Technology on Analog Integrated Circuit Laboratory | Chen X.,Science and Technology on Analog Integrated Circuit Laboratory
Advanced Materials Research | Year: 2013

In this paper, a kind of novel DAC architecture is proposed. Compared to the traditional DAC architecture, the proposed is a multistage one. In order to improve precision, we use a kind of feedback bias circuit, which can minimize the effect of the base currents. A 16-bit DAC transistor-level circuit is implemented in 0.18um SiGe process. The simulation results show that the DAC using the proposed architecture has higher resolution, and better static and dynamic performances than the traditional one. © (2013) Trans Tech Publications, Switzerland.


Zhang Z.-P.,China Electronics Technology Group Corporation | Wang Y.-L.,Science and Technology on Analog Integrated Circuit Laboratory | Huang X.-F.,Science and Technology on Analog Integrated Circuit Laboratory
ASID 2011 - Proceedings: 2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification | Year: 2011

A high-speed 8-bit analog-to-digital converter in 0.35m BiCMOS process technology is presented. The ADC uses the unique folding and interpolating architecture and the dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2GSPS. In case of digital calibration, as a result of testing, the ADC achieves 7.32ENOB at analog input of 484MHz, and 7.1ENOB at Nyquist input after the chip is self-corrected. © 2011 IEEE.


Zhu C.,Science and Technology on Analog Integrated Circuit Laboratory | Hu R.B.,Science and Technology on Analog Integrated Circuit Laboratory
Advanced Materials Research | Year: 2014

For the first time, the capacitive non-linearity is considered and calibrated. Based on the traditional bootstrapped switch, a cell is added to eliminate the first-order capacitive non-linearity. The measurement shows that the sampling and holding circuit using the improved bootstrapped switch can achieve a SFDR of 86dB with respect to 76dB for the traditional one. © (2014) Trans Tech Publications, Switzerland.

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