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SUNNYVALE, CA, United States

Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 150.00K | Year: 2010

This Small Business Innovative Research (SBIR) Phase I project will demonstrate the feasibility of using model-based control of temperature and stress for millisecond flash annealing of semiconductor wafers. In response to the demand for ever faster chips that consume less power, the tools for fabrication of integrated circuits (IC's) are required to provide increasingly precise control of the manufacturing process, e.g., control of the transient wafer temperature during thermal processing. The manufacture of an IC involves hundreds of steps. One of these steps is thermal annealing used for dopant activation, a critical step in IC chip manufacturing. Next-generation IC's need very shallow and abrupt junctions that require annealing over shorter time periods and at higher temperatures, which is not possible with current conventional spike annealing equipment. Millisecond annealing with pulsed flash-lamps has the potential to meet the new annealing requirements. However, challenges related to reproducibility and stress-induced wafer damage must be overcome before flash anneal can be used in high-volume manufacturing. The project proposes to develop and commercialize a control software product to help accelerate the transition of flash anneal to the semiconductor industry. The broader impact/commercial potential of this project is in its ability to help enable widespread adoption of flash anneal during semiconductor wafer processing. There is a significant potential for millisecond flash anneal to complement and eventually replace conventional lamp-based Rapid Thermal Processing (RTP) for some important steps in semiconductor manufacturing. The RTP market has reached close to $308 million in 2008, and is expected to grow significantly in the future. The proposed product will enable flash annealing to meet the formidable process control requirements and economic metrics, and help transition it to high-volume manufacturing. This will benefit customers and will in turn benefit the IC makers and ultimately benefit US consumers with smaller, faster, lower power devices. These innovations will make a significant contribution to advancing production technologies for future microelectronic devices, which will benefit the society at large.

Agency: NSF | Branch: Standard Grant | Program: | Phase: | Award Amount: 150.00K | Year: 2011

This Small Business Innovation Research (SBIR) Phase I project aims to demonstrate the feasibility of rapid in-line detection of visible (macro) defects on wafers in semiconductor industry. The semiconductor manufacturing industry is a major contributor to the U.S. economy. Chips produced by this industry are used in a broad range of devices including PCs and cell phones. There are about 500 processing steps involved in fabrication of a typical chip using dozens of processing equipment. Defects may be introduced anywhere in the processing chain. This project catch large (macro) defects that are visible to human eye as soon as they occur. The idea uses off-the-shelf scanner technology but sophisticated image processing algorithms to detect and classify such faults and identify remedies to fix the faulty equipment right away before any further processing. This approach will significantly reduce costs and increase the output of fabs by minimizing the production of bad chips. This equipment can be inserted throughout the fabrication plant and catches faults without disrupting wafer processing. Wide adoption of this technology can provide significant savings and provide the U.S. semiconductor industry with a competitive advantage.

The commercial potential of this project is enabling widespread adoption of macro-defect detection at every step and every wafer in semiconductor manufacturing. There is substantial potential in the semiconductor industry for an inexpensive tool for real-time detection of macro defects right at the equipment where the defect is generated. The successful commercialization of the proposed defect detection tool will assist in significantly increasing manufacturing yields and thus lowering costs. The global semiconductor defect-detection market has experienced significant growth over the past decade with the total market for automated test equipment expected to exceed $2 billion in 2010. This product will find use in several other secondary markets such as MEMS, solar energy devices, LED, photonics, etc. Finally, microelectronics affects almost every aspect of our lives. Hence, a product that makes a significant contribution to lowering the cost of manufacturing ICs will positively affect the society at large.

Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase I | Award Amount: 100.00K | Year: 2008

This SBIR Phase I project will develop model-based control of electro-chemical mechanical planarization systems used for future generations of semiconductor manufacturing. The model-based control will incorporate critical system knowledge to improve wafer uniformity and system throughput. The successful completion of this project will assist in the adoption new dielectric structures for next generation electronic devices. It may also enhance the understanding of electropolishing and electroplating processes. Optimization of the processes will also reduce environmentally sensitive waste.

Agency: NSF | Branch: Standard Grant | Program: | Phase: AISL | Award Amount: 2.70M | Year: 2012

This broad implementation project will create a professional network and community of practice for implementing Teen Cafes that engage high school teens in STEM. The Café Scientifique model for engaging adults in science has proven very effective and has been widely implemented. This project builds on a new successful model for Teen Cafes implemented over the past five years in New Mexico (NSF award 0714762).

Over 5 years the model will be scaled up in eight diverse regions across the country focusing particularly where there are large numbers of underrepresented teens. Core partners include Science Education Solutions in New Mexico; Southern Illinois University Edwardsville; the Florida Teen SciCafe Partnership; North Carolina Museum of Natural Science; and Science Discovery at the University of Colorado.

The project will build capacity for a broad range of ISE and STEM communities by encouraging and nurturing others wishing to start a Café program and join the network. The evaluation will study the impacts of both the local Teen Café sites as well as the national network. The evaluation of the local Café sites will analyze the challenges and opportunities when setting up local Cafes and how they are addressed; how well the national networks resources and support meet local needs; and how local adaptations affect outcomes for teens and professional audiences. The evaluation of the national network focuses on the processes for facilitating communication and management across the sites; the usefulness of the resources provided to sites; and the sustainability of the community of practice.

Agency: National Science Foundation | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 476.69K | Year: 2009

This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5). This Small Business Innovation Research (SBIR) Phase II project will develop a commercial prototype of a real-time model-based controller software for next-generation Chemical-Mechanical Planarization(CMP) systems used in semiconductor wafer manufacturing. Planarization is an enabling step for semiconductor interconnects that is critical to the industry's keeping up with Moore's law. Future technology nodes of 32 nm and below require improved level of performance in planarization technology. Smaller dimensions and the use of more delicate low-k films pose increasingly stringent requirements on planarization performance. The successful development of the proposed controller software will help extend planarization to new levels of performance for 32 nm technology and beyond. The copper planarization market is anticipated to reach $824 million in 2009, and a next-generation CMP controller product will have a significant impact on the future of this market. The proposed innovations will help to accelerate the adoption of new dielectric structures in next-generation semiconductor devices.

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