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Milpitas, CA, United States

Chen X.,SanDisk Corporation | Wang C.-L.,LSI Corporation
IEEE Transactions on Circuits and Systems I: Regular Papers | Year: 2012

Non-binary low-density parity-check (NB-LDPC) codes are robust to various channel impairments. The excessive computational complexity and memory usage of the existing decoder designs are considerably expensive for practical applications. Based on a newly proposed simplified min-sum algorithm, which only has 0.05-0.1 dB performance loss against the sum-product algorithm, a highly efficient decoder architecture is developed. Compared with the existing works, our design has three advantages. First, the design increases the parallelism and throughput of the decoder by three to four times. The implementation results for the decoder show high throughput of 64 Mbps at 15 iterations. Second, this design saves memory usage by 38% to 76%. Third, this design shows 2.64× area efficiency improvement even compared with the most state-of-the-art design. © 2012 IEEE. Source

Harari E.,SanDisk Corporation
Digest of Technical Papers - IEEE International Solid-State Circuits Conference | Year: 2012

In the past two decades Flash memory grew from a novelty technology to a powerful disruptor that has profoundly transformed consumer electronics and mobile computing. This was made possible through relentless cost reductions leveraging technology scaling through 19 generations of Flash memory in just 24 years, outpacing Moore's Law. © 2012 IEEE. Source

SanDisk Corporation | Date: 2014-01-24

Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation.

Methods are provided for forming a nanostructure array. An example method includes providing a first layer, providing nanostructures dispersed in a solution comprising a liquid form of a spin-on-dielectric, wherein the nanostructures comprise a silsesquioxane ligand coating, disposing the solution on the first layer, whereby the nanostructures form a monolayer array on the first layer, and curing the liquid form of the spin-on-dielectric to provide a solid form of the spin-on-dielectric. Numerous other aspects are provided.

SanDisk Corporation | Date: 2014-08-05

A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST).

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