Dublin, Ireland
Dublin, Ireland

Time filter

Source Type

Erdmann C.,Saggart Co. | Lowney D.,Saggart Co. | Lynam A.,Saggart Co. | Keady A.,Saggart Co. | And 12 more authors.
IEEE Journal of Solid-State Circuits | Year: 2015

A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35 mm 2 CS-BGA package. One mixed signal die consists of sixteen 16 bit current steering DACs, the other die consists of sixteen 13 bit pipelined ADCs. The interposer provides optimal system partitioning; noise isolation and high density interconnect between subsystems. Receive SNDR > 61.6 dBFS to Nyquist at 500 MS/s and transmit SFDR > 63.8 dBc to 400 MHz at 1.6 GS/s is measured. Ultralow FPGA to converter die interface power of 0.3 mW/Gb/s is achieved and measured digital to analog isolation > 92dB. The solution can be dynamically optimized for channel count, power and speed. © 1966-2012 IEEE.

Loading Saggart Co. collaborators
Loading Saggart Co. collaborators