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Kargaran E.,Sadjad Institute for Higher Education | Gorji G.,University of Tehran | Zargharni M.,Sadjad Institute for Higher Education | Emadi M.,University of Yazd
Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 | Year: 2010

A 3.1-10.6 GHz u1tra-wideband (UWB) low noise amplifier (LNA) utilizing a simple high-pass input matching network is proposed. The broadband matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF), good linearity, and the lower power consumption are also desired. The LNA is designed in the standard 0.18μm CMOS technology. The input reflection coefficient S11 and output reflection coefficient S12 are less than -7.8dB and -lIdB. It achieved maximum power gain 10 dB and the minimum noise figure is 1.7SdB. It consumes 12mW from a 1.8-V supply voltage. The designed system demonstrates relatively suitable response in different temperature and Variation 10% supply voltage. © 2010 IEEE.


Kargaran E.,Sadjad Institute for Higher Education | Kazemi M.M.,Khayam Institute for Higher Education
Proceedings of Papers - 5th European Conference on Circuits and Systems for Communications, ECCSC'10 | Year: 2010

An integrated 5 GHz low noise amplifier suitable for ultra low voltage and ultra low power applications is designed and simulated in a standard 0.18μm CMOS technology. By employing the current reuse and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 12 dB with a noise figure of 3.7 dB, while consuming only 450μW dc power with an ultra low supply voltage of 0. 5 V. The power consumption figure of merit(FOM1) and the tuning-range figure of merit(FOM2) are optimal at 26.67 dB/mw and 7.58(v.mw)-1, respectively.


Rasekh H.,Sadjad Institute for Higher Education | Sadeghi M.,Sadjad Institute for Higher Education | Golmakani A.,Sadjad Institute for Higher Education | Ali M.,Hail University
Proceedings - 2014 3rd Mediterranean Conference on Embedded Computing, MECO 2014 - Including ECyPS 2014 | Year: 2014

The predominant concern for SRAM cell designers is stability for nano-scaled technology due to the reduction in power supply voltages. We propose two novel SRAM cells, based on the Schmitt Trigger at 65 nm feature size in CMOS. This achieves 4-5.35 times higher read static noise margin (VDD = 350 mV) compared to the conventional 6T cell design. It also provides the much desired greater enhancement in stability compared with three other reported SRAM cell designs.


Golmakani A.,Sadjad Institute for Higher Education | Mafinejad K.,Sadjad Institute for Higher Education | Mafinejad K.,Ferdowsi University of Mashhad | Kouzani A.,Deakin University
International Journal of RF and Microwave Computer-Aided Engineering | Year: 2010

An important problem in designing RFIC in CMOS technology is the parasitic elements of passive and active devices that complicate design calculations. This article presents three LNA topologies including cascode, folded cascade, and differential cascode and then introduces image rejection filters for low-side and high-side injection. Then, a new method for design and optimization of the circuits based on a Pareto-based multiobjective genetic algorithm is proposed. A set of optimum device values and dimensions that best match design specifications are obtained. The optimization method is layout aware, parasitic aware, and simulation based. Circuit simulations are carried out based on TSMC 0.18 lm CMOS technology by using Hspice. © 2010 Wiley Periodicals, Inc.


Dadamahalleh K.A.,Sadjad Institute for Higher Education | Hodtani G.A.,Ferdowsi University of Mashhad
IEEE International Symposium on Information Theory - Proceedings | Year: 2013

In this paper we derive a new upper bound for the input-output mutual information of FSO channels with input-dependent Gaussian noise by using a simple mathematical inequality. Then, by maximizing the obtained upper bound over all the discrete input distributions with equally spaced mass points, and approximating, we reach to a third order equation for the optimum input distribution. Our equation (i) determines the optimum input distribution directly in contrary to the Farid-Hranilovic (FH) work where it is found numerically, and also, (ii) gives a previously derived second order equation for the optimum input distribution of FSO channels with input-independent Gaussian noise in a special case. Using numerical illustrations, we compare our input distribution with previous works. © 2013 IEEE.


Kargaran E.,Sadjad Institute for Higher Education | Khosrowjerdi H.,Sadjad Institute for Higher Education | Ghaffarzadegan K.,Sadjad Institute for Higher Education
ICMEE 2010 - 2010 2nd International Conference on Mechanical and Electronics Engineering, Proceedings | Year: 2010

A High Swing Ultra-Low-Power Two Stage CMOS OP-AMP in 0.18 μm Technology with 1.5v supply, is presented. Topology selection and theoretical analysis of the design are discussed. Cascode technique has been used to increase the dc gain. The unity-gain bandwidth is also enhanced using a gain-stage in the Miller capacitor feedback path. The proposed opamp provides 236MHz unity-gain bandwidth, 81.3 degree phase margin and a peak to peak output swing 1.26v. The circuit has 92.5dB gain and slew rate is 16.75 v/μs. The power dissipation of the designed only is 50μw. The designed system demonstrates relatively suitable response in different temperature. © 2010 IEEE.


Sheikholeslami M.M.,Sadjad Institute for Higher Education | Deihimfar H.R.,Sadjad Institute for Higher Education | Mafinezhad K.,Sadjad Institute for Higher Education | Akhlaghi I.A.,Sadjad Institute for Higher Education
Advanced Materials Research | Year: 2013

Micro-electromechanical switches (MEMS) with good performance in high frequency application such as linearity, no DC power consumption, no noise, small size and capability to co-fabrication on the chip today, it is noteworthy. the evolutionary approach in the design optimization of MEMS is a novel and promising research area. The problem is of a multi-objective nature; hence, multi-objective evolutionary algorithms (MOEA) are used. In this paper we introduced geometrical parameters of micro-electromechanical switch as input parameters or variables of multi-objective genetic algorithms then we compute electrical parameter of mems switch That show good performance and relation between theoretical parameter and simulated results is good. © (2013) Trans Tech Publications, Switzerland.


Kargaran E.,Sadjad Institute for Higher Education | Khosrowjerdi H.,Sadjad Institute for Higher Education | Ghaffarzadegan K.,Sadjad Institute for Higher Education | Kenarroodi M.,Sadjad Institute for Higher Education
Proceedings of Papers - 5th European Conference on Circuits and Systems for Communications, ECCSC'10 | Year: 2010

In this paper, a novel high gain two stage Ultra wideband (UWB) Low Noise Amplifier (LNA) typology is proposed. The broadband matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF), good linearity, and the lower power consumption are also desired. The common gate input stage configuration is used in the proposed LNA to achieve the broadband input matching. The flat gain of the LNA are achieved by the shunt inductor insertion between the cascade stages of LNA and series inductor insertion between two stage. A bias resistor of large value is placed between source and the body node to prevent body effect and reduce noise. The LNA is designed in the standard 0.18μm CMOS technology. The input and output reflection coefficient are less than -12.5dB and -8dB, respectively. It achieved maximum power gain 13.1dB, minimum noise figure is 3.35dB and maximum IIP3 is -7dBm. It consumes 10.7mW from a 1.8-V supply voltage.


Mir M.,Quchan Institute of Engineering and Technology | Ebrahimnia-Bajestan E.,Ferdowsi University of Mashhad | Niazmand H.,Ferdowsi University of Mashhad | Mir M.,Sadjad Institute for Higher Education
Computational Materials Science | Year: 2012

In this paper, a continuum model is presented to investigate the thermal properties of carbon nanotubes (CNTs). The proposed model considers each carbon-carbon (C-C) bond in CNT as a continuum solid element. The thermal properties of the CNTs can be calculated simply by computing the thermal properties of these solid elements. Considering a thermal resistance for each continuum solid element (C-C bond), equivalent thermal resistance of CNTs can be obtained which is used to determine the thermal conductivity of CNT. In order to find the thermal properties of C-C bond, Debye model has been utilized to calculate the specific heat capacity and thermal conductivity. Then, extended calculations have been carried out to study the thermal conductivity of armchair nanotube (10, 10) and its variations with temperature. © 2012 Elsevier B.V. All rights reserved.


Karimi M.,Sadjad Institute for Higher Education | Nabovati H.,Sadjad Institute for Higher Education
2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011 | Year: 2011

A highly efficient fully integrated passive CMOS rectifier is proposed in this paper. Using four ultra low power and low voltage techniques with proper leakage current compensation technique, this new topology is very high efficient in wide input voltage range of both high voltages and low voltage advanced sub-micron applications simultaneously. In 0.5V AC input signal amplitude the power and voltage transmission efficiency are 58% and 62% respectively and these values reach to 68% and 72% in 0.8V. Unlike the recently proposed rectifiers, in this new rectifier, for wide range of AC input signal amplitude the power and voltage transmission efficiency are higher than 90%. New proposed rectifier is applicable for bio-implantable systems with high current demands. The new full-wave rectifier also simulated and optimized only for low voltage advanced sub-micron applications. This rectifier designed and simulated in 0.18μm standard CMOS technology. © 2011 IEEE.

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