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Dadamahalleh K.A.,Sadjad Institute for Higher Education | Hodtani G.A.,Ferdowsi University of Mashhad
IEEE International Symposium on Information Theory - Proceedings | Year: 2013

In this paper we derive a new upper bound for the input-output mutual information of FSO channels with input-dependent Gaussian noise by using a simple mathematical inequality. Then, by maximizing the obtained upper bound over all the discrete input distributions with equally spaced mass points, and approximating, we reach to a third order equation for the optimum input distribution. Our equation (i) determines the optimum input distribution directly in contrary to the Farid-Hranilovic (FH) work where it is found numerically, and also, (ii) gives a previously derived second order equation for the optimum input distribution of FSO channels with input-independent Gaussian noise in a special case. Using numerical illustrations, we compare our input distribution with previous works. © 2013 IEEE.

Kargaran E.,Sadjad Institute for Higher Education | Kazemi M.M.,Khayam Institute for Higher Education
Proceedings of Papers - 5th European Conference on Circuits and Systems for Communications, ECCSC'10 | Year: 2010

An integrated 5 GHz low noise amplifier suitable for ultra low voltage and ultra low power applications is designed and simulated in a standard 0.18μm CMOS technology. By employing the current reuse and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 12 dB with a noise figure of 3.7 dB, while consuming only 450μW dc power with an ultra low supply voltage of 0. 5 V. The power consumption figure of merit(FOM1) and the tuning-range figure of merit(FOM2) are optimal at 26.67 dB/mw and 7.58(v.mw)-1, respectively.

Rasekh H.,Sadjad Institute for Higher Education | Sadeghi M.,Sadjad Institute for Higher Education | Golmakani A.,Sadjad Institute for Higher Education | Ali M.,Hail University
Proceedings - 2014 3rd Mediterranean Conference on Embedded Computing, MECO 2014 - Including ECyPS 2014 | Year: 2014

The predominant concern for SRAM cell designers is stability for nano-scaled technology due to the reduction in power supply voltages. We propose two novel SRAM cells, based on the Schmitt Trigger at 65 nm feature size in CMOS. This achieves 4-5.35 times higher read static noise margin (VDD = 350 mV) compared to the conventional 6T cell design. It also provides the much desired greater enhancement in stability compared with three other reported SRAM cell designs.

Kargaran E.,Sadjad Institute for Higher Education | Gorji G.,University of Tehran | Zargharni M.,Sadjad Institute for Higher Education | Emadi M.,University of Yazd
Proceedings - 2010 3rd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2010 | Year: 2010

A 3.1-10.6 GHz u1tra-wideband (UWB) low noise amplifier (LNA) utilizing a simple high-pass input matching network is proposed. The broadband matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF), good linearity, and the lower power consumption are also desired. The LNA is designed in the standard 0.18μm CMOS technology. The input reflection coefficient S11 and output reflection coefficient S12 are less than -7.8dB and -lIdB. It achieved maximum power gain 10 dB and the minimum noise figure is 1.7SdB. It consumes 12mW from a 1.8-V supply voltage. The designed system demonstrates relatively suitable response in different temperature and Variation 10% supply voltage. © 2010 IEEE.

Golmakani A.,Sadjad Institute for Higher Education | Mafinejad K.,Sadjad Institute for Higher Education | Mafinejad K.,Ferdowsi University of Mashhad | Kouzani A.,Deakin University
International Journal of RF and Microwave Computer-Aided Engineering | Year: 2010

An important problem in designing RFIC in CMOS technology is the parasitic elements of passive and active devices that complicate design calculations. This article presents three LNA topologies including cascode, folded cascade, and differential cascode and then introduces image rejection filters for low-side and high-side injection. Then, a new method for design and optimization of the circuits based on a Pareto-based multiobjective genetic algorithm is proposed. A set of optimum device values and dimensions that best match design specifications are obtained. The optimization method is layout aware, parasitic aware, and simulation based. Circuit simulations are carried out based on TSMC 0.18 lm CMOS technology by using Hspice. © 2010 Wiley Periodicals, Inc.

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