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Ossining, NY, United States

Suarez E.,University of Connecticut | Gogna M.,University of Connecticut | Al-Amoody F.,University of Connecticut | Karmakar S.,University of Connecticut | And 3 more authors.
Journal of Electronic Materials | Year: 2010

This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn 0.95Mg 0.05S/ZnS tunnel insulators. The GeO x-cladded Ge and SiO x-cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudo- morphic II-VI stack serves both as a tunnel insulator and a high-κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si 3N 4 and SiO 2 layers grown by plasma- enhanced chemical vapor deposition. © 2010 TMS. Source


Jain F.C.,University of Connecticut | Miller B.,University of Connecticut | Suarez E.,University of Connecticut | Chan P.-Y.,University of Connecticut | And 5 more authors.
Journal of Electronic Materials | Year: 2011

This paper presents the implementation of a novel InGaAs field-effect transistor (FET), using a ZnSe-ZnS-ZnMgS-ZnS stacked gate insulator, in a spatial wavefunction-switched (SWS) structural configuration. Unlike conventional FETs, SWS devices comprise two or more asymmetric coupled quantum wells (QWs). This feature enables carrier transfer vertically from one quantum well to another or laterally to the wells of adjacent SWS-FET devices by manipulation of the gate voltages (V g). Observation of an extra peak (near both accumulation and inversion regions) in the capacitance-voltage data in an InGaAs-AlInAs two-quantum-well SWS structure is presented as evidence of spatial switching. The peaks are attributed to the appearance of carriers first in the lower well and subsequently their transfer to the upper well as the gate voltage is increased. The electrical characteristics of a fabricated SWS InGaAs FET are also presented along with simulations of capacitance-voltage (C-V) behavior, showing the effect of wavefunction switching between wells. Finally, logic operations involving simultaneous processing of multiple bits in a device, using coded spatial location of carriers in quantum well channels, are also described. © 2011 TMS. Source


Jain F.C.,University of Connecticut | Chandy J.,University of Connecticut | Miller B.,University of Connecticut | Hasaneen E.-S.,Minia University | Heller E.,RSoft Design Group
International Journal of High Speed Electronics and Systems | Year: 2011

Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs-AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n-channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed. © 2011 World Scientific Publishing Company. Source


Jain F.,University of Connecticut | Karmakar S.,University of Connecticut | Chan P.-Y.,University of Connecticut | Suarez E.,University of Connecticut | And 3 more authors.
Journal of Electronic Materials | Year: 2012

This paper describes fabrication and modeling of quantum dot channel (QDC) field-effect transistors (FETs). A QDC-FET comprises an array of thin-barrier (∼1 nm) cladded Si, Ge, or other quantum dots (3 nm to 4 nm) forming an n-channel on a p-Si layer/substrate between the source and drain regions. Experimental characteristics of fabricated QDC-FETs, consisting of two layers of cladded quantum dot arrays (e.g., SiO x-cladded Si dots and GeO x-cladded Ge dots) serving as the transport channel, are presented. Unlike conventional FETs, QDC-FET structures exhibit step-like I D-V G characteristics and discretely bunched I D-V D characteristics as a function of gate voltage. The transfer characteristics appear to be similar to those of single-electron transistors (SETs). However, QDC-FETs employ transport of many electrons and operate at room temperature. A one-dimensional Tsu-Esaki equation is used to simulate the quantum dot channel and explain the steps in the current-voltage behavior. In particular, the effect of the II-VI barrier layers on Ge dots is modeled. The QDC-FET channel is also modeled as having superlattice-like mini-energy bands whose bandwidth and separation are determined by the dot size, cladding thickness, and barrier height. For a given gate voltage (which determines the carrier concentration), carriers in the inversion channel are transported via mini-energy bands that line up with the Fermi level as the drain voltage V DS is changed, producing step-like multistate electrical characteristics. Formation of the quantum dot channel enables higher-mobility transport on very low-mobility substrates or thin films such as poly-Si. The channel mobility can be further enhanced by partially removing the oxide barrier layer and replacing it with lattice-matched II-VI gate insulator layers. © 2012 TMS. Source


Grant
Agency: Department of Defense | Branch: Navy | Program: STTR | Phase: Phase I | Award Amount: 79.69K | Year: 2011

We proposed to perform innovative research towards the developing of a simulation tool consisting of a comprehensive set of models and including modeling techniques that account for the complex interactions between optical network components in WDM LANs, such as those planned for aerospace platforms. To a large extent, the modeling effort will be guided by the ongoing work of the AS-3 WDM LAN working group, with experimental validation to be conducted later in Phase II through a testbed that is applicable to the development activities of the SAE AS-5659 industry standard open architecture. Specifically, Phase I will specify a technique to model optical return loss (ORL) in a system simulation tool, such as OptSim from RSoft Design Group; determine the nature of the complex interactions in WDM LANs resulting from the interplay of optical amplification, ORL, and transients due to amplifier gain dynamics and channel equalization in a multiwavelength network; specify a flexible set of OptSim simulation options and corresponding software configurations that allow the simulation technique to be based on either wavelength-domain simulation (WDS), full waveform (time-domain) simulation, or a combination of WDS and waveform simulation; specify requirements and software modules for a WDM LAN planning tool based on RSoft"s MetroWAND network planning tool; and specify key experiments to validate the modeling techniques during the Phase II effort.

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