Tominaga S.,Roki Techno Co. |
Abe D.,Roki Techno Co. |
Enomoto T.,Roki Techno Co. |
Kondo S.,Roki Techno Co. |
And 5 more authors.
Japanese Journal of Applied Physics | Year: 2010
A hybrid electrochemical mechanical planarization and chemical mechanical planarization (e-CMP/CMP) was applied to the Cu dual-damascene through-silicon via (TSV) process for wafer-level three-dimensional integrated circuit (3D-IC) stacking. In this process, an electrochemically deposited Cu film was removed by e-CMP at a removal rate of 3.5μm/min until the voltage endpoint was detected. Then, residual Cu film was polished off in the CMP mode using the same e-CMP pad. A fine Cu damascene structure was successfully fabricated with a dishing depth of less than 200nm in a metal pad of 200 × 200 μm 2 area. The criterion of dishing without failure in the adhesive coat for 3D-IC stacking is discussed. © 2010 The Japan Society of Applied Physics.
Roki Techno Co. | Date: 2013-01-16
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