Time filter

Source Type

Guangzhou, China

Xu K.,South China University of Technology | Xu K.,Rising Micro Electronics Co. | Cai M.,South China University of Technology
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014

This paper presents a 3rd-order continuous-time (CT) Delta-Sigma modulator (DSM) for broadband digital transceivers. In this design, a low-cost Proportional-Integrating (PI) element Excess Loop Delay (ELD) compensation method is adopted to mitigate the influence of ELD. Meanwhile, to avoid the compensation zero and loop filter coefficients variation due to process variation, an on-chip automatic RC constant tuning block is used to trim the RC constant. The proposed DSM is fabricated in a 0.13 um 1P6M CMOS technology and occupies an active area of 0.22 mm2. It achieves 68 dB dynamic range (DR), 66 dB peak signal to noise plus distortion ratio (SNDR) in 10 MHz bandwidth under 500MHz sampling frequency and dissipates 13 mW power under 1.5 V power supply. © 2014 IEEE. Source

Huang M.,Sun Yat Sen University | Huang M.,Rising Micro Electronics Co. | Huang M.,SYSU CMU Shunde International Joint Research Institute | Chen D.,Sun Yat Sen University | And 9 more authors.
Microelectronics Journal

In this work, a tri-band (Band 39: 1880-1920 MHz, Band 40: 2300-2400 MHz, and Band 38: 2570-2620 MHz), 2-receiver (RX) multiple-in-multiple-out (MIMO), 1-transmitter (TX) TD-LTE (Time Division Long Term Evolution) CMOS transceiver is presented and fabricated in 0.13-μm CMOS technology. The continuous-time delta-sigma A/D converters (CT ΔΣ ADCs) are directly coupled to the RX front-end outputs to achieve low power. With proper gain allocation and a novel carrier leakage calibration, the TX section ensures at least -40 dBc carrier leakage suppression over 86-dB gain range. The transceiver dissipates maximum 171 mW at 2-RX MIMO mode and 183 mW at 1-TX maximum gain mode. To the best of our knowledge, this is the first research paper on fully integrated commercial TD-LTE transceiver. © 2014 Elsevier Ltd. All rights reserved. Source

Huang M.,Sun Yat Sen University | Chen D.,Sun Yat Sen University | Wang Z.,Sun Yat Sen University | Guo J.,Sun Yat Sen University | And 8 more authors.
International Journal of Circuit Theory and Applications

In this work, a power-area-efficient, 3-band, 2-RX MIMO, and TD-LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD-SCDMA) CMOS receiver is presented and implemented in 0.13-μm CMOS technology. The continuous-time delta-sigma A/D converters (CT ΔΣ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti-aliasing filters between RX front-end and ADCs in conventional structures. The strong adjacent channel interference without low-pass filter attenuation is handled by proper gain control. A low-power small-area solution for excess loop delay compensation is implemented in the CT ΔΣ ADC. At 20 MHz bandwidth, the CT ΔΣ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal-to-noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low-pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2-RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD-LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd. Source

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