Rising Micro Electronics Co.

Guangzhou, China

Rising Micro Electronics Co.

Guangzhou, China
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Liang Z.,South China University of Technology | Liang Z.,Rising Micro Electronics Co. | Li B.,South China University of Technology | Huang M.,South China University of Technology | And 6 more authors.
Sensors (Switzerland) | Year: 2017

In this work, a low cost Bluetooth Low Energy (BLE) transceiver for wireless sensor network (WSN) applications, with a receiver (RX)-matching network-reusing power amplifier (PA) load inductor, is presented. In order to decrease the die area, only two inductors were used in this work. Besides the one used in the voltage control oscillator (VCO), the PA load inductor was reused as the RX impedance matching component in the front-end. Proper controls have been applied to achieve high transmitter (TX) input impedance when the transceiver is in the receiving mode, and vice versa. This allows the TRX-switch/matching network integration without significant performance degradation. The RX adopted a low-IF structure and integrated a single-ended low noise amplifier (LNA), a current bleeding mixer, a 4th complex filter and a delta-sigma continuous time (CT) analog-to-digital converter (ADC). The TX employed a two-point PLL-based architecture with a non-linear PA. The RX achieved a sensitivity of – 93 dBm and consumes 9.7 mW, while the TX achieved a 2.97% error vector magnitude (EVM) with 9.4 mW at 0 dBm output power. This design was fabricated in a 0.11 μm complementary metal oxide semiconductor (CMOS) technology and the front-end circuit only occupies 0.24 mm2. The measurement results verify the effectiveness and applicability of the proposed BLE transceiver for WSN applications. © 2017 by the authors. Licensee MDPI, Basel, Switzerland.


Liu Y.,East China Jiaotong University | Deng F.,East China Jiaotong University | Deng F.,Hefei University of Technology | He Y.,Hefei University of Technology | And 3 more authors.
Sensors (Switzerland) | Year: 2017

This paper firstly introduces the importance of temperature control in concrete measurement, then a passive radio frequency identification (RFID) sensor tag embedded for concrete temperature monitoring is presented. In order to reduce the influences of concrete electromagnetic parameters during the drying process, a T-type antenna is proposed to measure the concrete temperature at the required depth. The proposed RFID sensor tag is based on the EPC generation-2 ultra-high frequency (UHF) communication protocol and operates in passive mode. The temperature sensor can convert the sensor signals to corresponding digital signals without an external reference clock due to the adoption of phase-locked loop (PLL)-based architecture. Laboratory experimentation and on-site testing demonstrate that our sensor tag embedded in concrete can provide reliable communication performance in passive mode. The maximum communicating distance between reader and tag is 7 m at the operating frequency of 915 MHz and the tested results show high consistency with the results tested by a thermocouple. © 2017 by the authors.


Liang Z.,South China University of Technology | Li B.,South China University of Technology | Huang M.,South China University of Technology | Ye H.,South China University of Technology | And 5 more authors.
2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 | Year: 2017

In this work, a four-band (Band 34 and Band 38-40) TD-LTE (Time Division-Long Term Evolution) transmitter (TX) is presented and fabricated in a 0.13μm CMOS technology. The TX adopted a direct up-conversion structure and integrated a fine digital variable gain amplifier (VGA), segmented R-2R ladder DACs, high linearity up-conversion mixers and wide dynamic range programmable gain amplifies (PGA). An optimized automatic bandwidth calibration circuits compensate a targeted 30% process variation. A 1.78% error vector magnitude (EVM) is achieved, with the adjacent channel power leakage (ACPL) ratio below -50dBc at 10MHz bandwidth, 16QAM modulation. The dynamic range of this TX exceeds 90dB with a fine step of 0.5dB, and the third harmonic distortion (HD3) achieves -54dBc. The TX dissipates 150mW at maximum output power. © 2017 IEEE.


Ye H.,South China University of Technology | Ye H.,Rising Micro Electronics Co. | Li B.,South China University of Technology | Huang M.,South China University of Technology | And 3 more authors.
2017 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2017 | Year: 2017

A low complexity digital IQ (in-phase and quadrature) imbalance self-calibration technique in Frequency Division Duplexing (FDD) transceiver is proposed in this paper. The RX (receiver) and TX (transmitter) IQ imbalance are compensated by a digital post-correction and pre-distortion, respectively, and the correction and distortion parameters can be accurately acquired in calibration mode while the transceiver starts up. The proposed digital self-calibration scheme has been implemented to a FDD transceiver in 0.13 μm CMOS process. The measurement shows that with the proposed calibration, 60dB image suppression is achieved in both RX and TX. This ensures a 2.12% and 2.3% EVM of 64QAM in RX and TX, respectively, comparing to 4.67% and 5.16% without the calibration. © 2017 IEEE.


Huang M.,Sun Yat Sen University | Huang M.,Rising Micro Electronics Co. | Huang M.,SYSU CMU Shunde International Joint Research Institute | Chen D.,Sun Yat Sen University | And 9 more authors.
Microelectronics Journal | Year: 2015

In this work, a tri-band (Band 39: 1880-1920 MHz, Band 40: 2300-2400 MHz, and Band 38: 2570-2620 MHz), 2-receiver (RX) multiple-in-multiple-out (MIMO), 1-transmitter (TX) TD-LTE (Time Division Long Term Evolution) CMOS transceiver is presented and fabricated in 0.13-μm CMOS technology. The continuous-time delta-sigma A/D converters (CT ΔΣ ADCs) are directly coupled to the RX front-end outputs to achieve low power. With proper gain allocation and a novel carrier leakage calibration, the TX section ensures at least -40 dBc carrier leakage suppression over 86-dB gain range. The transceiver dissipates maximum 171 mW at 2-RX MIMO mode and 183 mW at 1-TX maximum gain mode. To the best of our knowledge, this is the first research paper on fully integrated commercial TD-LTE transceiver. © 2014 Elsevier Ltd. All rights reserved.


Huang M.,Sun Yat Sen University | Chen D.,Sun Yat Sen University | Wang Z.,Sun Yat Sen University | Guo J.,Sun Yat Sen University | And 8 more authors.
International Journal of Circuit Theory and Applications | Year: 2015

In this work, a power-area-efficient, 3-band, 2-RX MIMO, and TD-LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD-SCDMA) CMOS receiver is presented and implemented in 0.13-μm CMOS technology. The continuous-time delta-sigma A/D converters (CT ΔΣ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti-aliasing filters between RX front-end and ADCs in conventional structures. The strong adjacent channel interference without low-pass filter attenuation is handled by proper gain control. A low-power small-area solution for excess loop delay compensation is implemented in the CT ΔΣ ADC. At 20 MHz bandwidth, the CT ΔΣ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal-to-noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low-pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2-RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD-LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.


Xu K.,South China University of Technology | Xu K.,Rising Micro Electronics Co. | Cai M.,South China University of Technology | Dagher E.H.,Rising Micro Electronics Co. | And 6 more authors.
Analog Integrated Circuits and Signal Processing | Year: 2016

This paper presents a low power and area-efficient 3rd-order continuous-time delta-sigma (CT ΔΣ) modulator for LTE/TD-SCDMA digital receivers. In the proposed modulator, the integrators’ coefficients are programmable to meet all LTE and TD-SCDMA signal bandwidths and dynamic range requirements. Moreover, to meet both the high performance and low-cost requirements, the proposed analog-to-digital converter (ADC) adopts: a low-cost excess loop delay compensation method, a non-return-to-zero feedback digital-to-analog converter (DAC) which is clocked by low-noise LC phase lock loop, an on-chip tuning scheme to reduce sensitivity to bandwidth variations, and dynamic element matching 9-level DACs. The CT ΔΣ modulator is designed and fabricated in a 0.13 μm 1-poly 6-metal standard CMOS technology and occupies an active area of 0.20 mm2. For all signal bandwidths of LTE/TD-SCDMA standards, the proposed ADC achieves 70–87 dB dynamic range, and 66–84 dB peak SNDR with 8.4–10.2 mW power consumption under 1.5 V power supply. © 2016, Springer Science+Business Media New York.


Xu K.,South China University of Technology | Xu K.,Rising Micro Electronics Co. | Cai M.,South China University of Technology
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014 | Year: 2014

This paper presents a 3rd-order continuous-time (CT) Delta-Sigma modulator (DSM) for broadband digital transceivers. In this design, a low-cost Proportional-Integrating (PI) element Excess Loop Delay (ELD) compensation method is adopted to mitigate the influence of ELD. Meanwhile, to avoid the compensation zero and loop filter coefficients variation due to process variation, an on-chip automatic RC constant tuning block is used to trim the RC constant. The proposed DSM is fabricated in a 0.13 um 1P6M CMOS technology and occupies an active area of 0.22 mm2. It achieves 68 dB dynamic range (DR), 66 dB peak signal to noise plus distortion ratio (SNDR) in 10 MHz bandwidth under 500MHz sampling frequency and dissipates 13 mW power under 1.5 V power supply. © 2014 IEEE.


Ken X.,South China University of Technology | Ken X.,Rising Micro Electronics Co. | Min C.,South China University of Technology | He X.,South China University of Technology | And 2 more authors.
Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015 | Year: 2015

This paper presents a novel low-cost automatic DC-Offset cancellation method and circuit for DAC in RF transmitter. The automatic DC-Offset cancellation block consists of one voltage comparator, one 5-bit R-2R auxiliary DAC and a SAR digital block. The proposed DC-Offset cancellation works during power-on sequence, then stores the value of control word in registers and shuts down the comparator and SAR block to save power after the cancellation operation. Unlike other methods, the proposed method has no influence on the desired signal, and does not disturb the work of transceiver. The proposed block is fabricated in 0.13um CMOS process as one sub-block of a RF transceiver. It occupies only 100um - 200um active area, and consumes only 100uA current under 1.2 V power supply. It is a low-cost solution for cancelling DC-Offset voltage both in receivers and transmitters. © 2015 IEEE.

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