Tucson, AZ, United States
Tucson, AZ, United States

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A test structure includes a dedicated addressing circuit that allows large numbers of test devices to be tested simultaneously and the measurement signals read out serially for different test devices. The test structure may be configured for wafer, die or package-level testing. The test structure may be integrated on a common die with the test devices in a single package, provided on separate die in a common package, separately packaged chips or in the form of a collection of standard die configured as the test structure. If on separate die, the test and addressing circuitry is fabricated from a more mature fabrication process than that being characterized for the devices under test. The processes being characterized may be unqualified whereas the test circuitry may be fabricated with different and more mature or qualified processes.


Grant
Agency: Department of Defense | Branch: Navy | Program: SBIR | Phase: Phase I | Award Amount: 79.99K | Year: 2014

The critical navigational precision of the nuclear-powered ballistic missile submarine fleet is based on the aging Electrostatically Supported Gyroscope Navigator (ESGN). The increasing frequency of repairs and increasing Mean Time To Repair (MTTR) for ESGN systems have potential to affect mission readiness. Ridgetop Group proposes an Expert Troubleshooting Action System (ETAS) to reduce mean time to repair (MTTR) and increase mean time between failures (MTBF). The novel machine learning system combines accelerated diagnostics with prognostics to detect signatures of incipient failure. This optimized approach enables simultaneous preventive and corrective maintenance within prescribed time-constraints. The diagnostic element builds on Ridgetop"s experience in prioritized analytical troubleshooting, anchored in historical repair actions and outcomes from existing best practices for the ESGN. Difficult-to-diagnose faults (e.g., intermittent connections and marginal stability) will receive particular focus. The prognostic element will integrate diagnostic data with"what-if"analyses and physics-of-failure models to identify likely next failures and corresponding time horizons. The prognostic element leverages Ridgetop"s core strengths in prognostic health management (PHM) and condition-based maintenance (CBM) for complex electronic and electromechanical equipment. Ridgetop will formulate metrics in Phase I to drive maturation of the approach in Phase II.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 750.00K | Year: 2015

ABSTRACT: The proposed program addresses the cost effectiveness of maintenance operations for mission-critical electronic warfare circuit card assemblies (CCAs), by reducing no fault found (NFF) codes and accelerating accurate diagnosis of root causes in support of repairs of analog, digital, radio frequency (RF) and mixed-signal CCAs. Benefits of the proposed work include a projected 50% reduction in mean time to repair (MTTR) rates, commensurate cost savings, and seamless integration with the Versatile Depot Automatic Test Station (VDATS) platform. Beginning with identification of"bad actor"CCAs with high potential return on investment, the effort is driven by expert analog and digital circuit analysis and informed by actual historical parts usage and repair data from the Lean Depot Management System (LDMS). The results of this data-enhanced analysis are codified in automated troubleshooting procedures implemented in software as augmented VDATS Test Program Sets (TPSs). BENEFIT: The primary benefits to the Air Force are reduced NFF, reduced MTTR, and reduced maintenance costs. Significantly, this is achieved with minimal training required, because the enhanced TPS software integrates with the existing VDATS workflow.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 750.00K | Year: 2015

ABSTRACT: Ridgetop Group, Inc. will develop an innovative solution to isolate troublesome no-fault-found (NFF) occurrences in the maintenance depot. We will develop advanced technology to integrate into improved Test Program Sets (TPSs) used to test complex circuit card assemblies (CCAs) of line-replaceable units (LRUs) in electronic warfare (EW) systems. The work will result in a 60% reduction in NFF rates, and a 55% reduction in mean time to repair (MTTR). The technology centers on detecting and locating difficult-to-troubleshoot electronic problems caused by analog degradation of digital data from aged CCAs identified as"bad-actor"CCAs. Each TPS used to test such CCAs is expanded to apply expert troubleshooting techniques that include exploiting test-and-measurement capabilities of VDATS (Versatile Depot Automatic Test Station) equipment at the Maintenance Depot located at Robins AFB. The"Expert Troubleshooting and Repair System"(ETRS) technology added to a TPS consists of the following: (1) expert troubleshooting support (ETS) for a prioritized list of selected bad-actor subcircuits in a bad-actor CCA; (2) each ETS consists of a sequence of tests to identify analog degradation of electronic signals and to pinpoint the source of any such degradation: chip, component (resistor, capacitor, inductor, and so on), or cable harness or cable connector; a test sequence includes test-dependent action(s), including recommended repair actions; and (3) a TPS is a sequence of multiple tests applicable to a specific CCA and written in National Instruments/CVI programming language. BENEFIT: There will be a set of improved TPSs developed for bad-actor circuit card assemblies that will identify, locate, and provide repair actions for difficult-to-diagnose problems caused by analog degradation of digital signals within those bad-actor CCAs. The integration and application of the improved TPSs will reduce the cost of service and maintenance, improve reliability of serviced CCAs when they are returned to the supply chain, and increase flight reliability and availability as summarized by the following: (1) a 60% reduction in no-fault-found (NFF) service codes; (2) a 75% reduction in time to isolate faults; (3) a 55% reduction in the mean time to repair (MTTR); and (4) a 50% reduction in unnecessary repair actions. The work products will be deployed to approximately 75 VDATS test stands in the Air Force to improve current test methodologies. Other related module test applications exist in the commercial sector where inadequate testing causes higher maintenance expenses.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase I | Award Amount: 149.45K | Year: 2014

ABSTRACT: Ridgetop Group will develop design tools to facilitate fabrication of obsolete, radiation-hardened, precision analog components. The methodology that is developed and validated during the nine-month Phase I SBIR program will be transitioned into an easy-to-use prototype software tool during Phase II. The Ridgetop EDA tool integrates well-known commercial EDA solutions to support radiation-hardened analog IC development. The first version will use Silvaco Atlas TCAD tool for radiation effect characterization, Cadence Spectre for SPICE circuit simulations, and Cadence APS for Verilog and Verilog-A simulations. Ridgetop"s own ProChek fabrication process characterization system will be integrated as a part of the tool flow to rapidly provide very valuable test data for optimum fabrication process selection, simulation model accuracy checks and RHBD structure validation. Cadence Virtuoso will be used for layout design, design rule checks and parasitic extraction. Overall flow control and automated generation of RHBD SPICE and layout files will be managed using Perl, a feature-rich scripting language. The tool can be used for generating hardened circuits for prompt dose rate effects, neutron effects, total ionizing dose and different types of single-event effects. This approach is a low-risk solution to the problem the Air Force has described in the solicitation topic. BENEFIT: Ridgetop has received valuable support from large satellite manufacturing companies and from NASA/JPL for the technology commercialization path. These companies and institutions are very interested in Ridgetop"s design flow innovation, since it can be used for rapid design of replacements for obsolete radiation-hardened components. By the same token, the tool can be used for converting existing"terrestrial"(not hardened) design schematics over to applications that have radiation tolerance requirements, which will result in significant cost savings since existing designs can now be reused. Potential commercial applications include: Military, scientific and commercial space systems Missile applications Cargo scanners Industrial radiation-hard instrumentation Medical devices Nuclear and high-energy physics applications


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 749.26K | Year: 2012

ABSTRACT: Ridgetop will develop an innovative Robustness Assessment for Design (RAD) tool for aircraft electrical power systems (EPS) to meet system safety, reliability, maintainability, and energy optimization requirements in each design stage by calculating system-level robustness. The design employs flow graph models for components at different hierarchies. The measurement of robustness takes into account the topology of the interconnected components, the degradation of the components from aging, and the environmental effects from field reliability data. In addition, factors associated with the following data are taken into account: X Real field data X Empirical data X Thermal and power data X System weight and failure modes and effects analysis (FMEA). The data are measured in multi-level hierarchical systems starting from the component level, and moving to the PWB level, the module level, up to the system level. The models can be connected in series, in parallel, and in combinations of both to conduct extensive Swhat-if analyses that optimize the design for overall system robustness improvement. The result of this SBIR program is a more accurate and modern alternative that maximizes system effectiveness, provides a reduction of energy consumption, and increases system robustness through more accurate estimates than those using conventional mean time between failures (MTBF)-type reliability calculations. BENEFIT: The anticipated benefits that Ridgetops technology offers are electrical power systems lifecycle improvement and continue level of performance in environment variations while optimizing energy. The main markets that will benefit from Ridgetops technology are the commercial aircraft, commercial aircraft maintenance, repair and overhaul (MRO), and potentially the automotive markets. In the military industry, the markets that will be benefited from this technology are the aerospace and defense and the unmanned aerial vehicles markets. This tool supports the demands for more reliable, robust, and energy optimized designs of electrical power systems. The competitive advantage of this technology over other electronic design automation (EDA) tools available in the market is its ability to provide more accurate estimates of systems-levels robustness over conventional mean time between failures (MTBF)-types of reliability calculations, which are largely based on parts population methods. Higher reliability, increased robustness for a variety of platforms, and energy efficiencies are the principal benefits that this tool offers.


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 750.00K | Year: 2012

ABSTRACT: In Phase II, Ridgetop Group will develop a high-performance radiation-hardened ADC suitable for use in satellite communication (SATCOM) systems where radiation exposure would otherwise degrade performance. This proposal responds to Air Force topic AF103-092, with the objective of designing a radiation-hardened, high speed (2 GSPS) analog-to-digital data converter (ADC) with high bit precision for use in low bit error rate (BER) 16-quadrature amplitude modulation (QAM) demodulator applications. The significance of this innovation is that high speed and high performance communication systems, incorporating QAM demodulator subsystems, require digitization with extremely high linearity and dynamic range to achieve system performance targets. With the added requirement of radiation hardness, the ADC is a critical chokepoint that must meet demanding standards. Accordingly, Ridgetop"s ADC will be highly linear with an INL and DNL of no more than 0.5 LSB, a flat gain of<0.1 dB, a channel-to-channel isolation of>80 dB, an operating temperature range of at least -40 to 80 degrees C, a very high effective number of bits (ENOB) of 11, and a TID tolerance better than 300 krad(Si). The proposed ADC can be used as an integral part of Air Force"s SATCOM low BER, 16 QAM demodulator applications. Ridgetop"s ADC is much more suitable for this purpose than currently commercially available ADCs due to its high radiation hardness and significant performance improvement compared to the radiation-hardened ADCs that are commercially available. BENEFIT: Precision data converters are critical to the performance of high-speed digital signal processing (DSP) systems. The sampling rate and resolution of the converters define the performance aspects of the entire system. Because of its aggressive 2 GSPS sampling rate, high ENOB (11 bits), and low power dissipation (720 mW), this ADC overcomes a significant barrier to higher performance communications systems. Ridgetop"s innovative time-interleaved silicon germanium (SiGe)-based ADC will improve the resolution, linearity, power consumption and radiation hardness of current state-of-the art ADCs used in advanced communication systems. As a modular, self-contained building block from a popular trusted foundry, this ADC will become an important library element in future system designs. High-performance ADCs are widely used in satellite communication systems, space-based radar applications, medical imaging devices, software-defined radio applications, linear power amplifiers, high-speed data acquisition applications, high-speed test and instrumentation equipment, and high-speed digital signal processing (DSP) systems.


Grant
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 1.01M | Year: 2012

Particle detectors for nuclear physics and high energy physics experiments require high performance, high sensitivity digitizers for read-out electronics. Analog-to-digital converters (ADCs) are used in such applications but limit experimental results because of a restrictive combination of speed, resolution, power, and radiation-hardness. Many instruments need very high channel counts, a costly requirement and a very difficult objective to achieve where densely packed electronics generate too much heat. General statement of how this problem or situation is being addressed. This Phase II will result in the design and fabrication of an innovative high-performance, ultra-low-power device that will incorporate 16 ADC channels on a single chip. Using radiation-hardened-by-design (RHBD) techniques and the novel topology developed and verified in Phase I, the ADC chip will be able to provide the linearity and resolution required for use in a wide range of experimental instrumentation at HEP facilities like RHIC and LHC, and in nuclear physics labs at Jefferson Lab, Oak Ridge, and others, while also lowering costs because of the high degree of channel density. What was done in Phase I? Phase I saw the design, development, and simulation of a behavioral model of the complete ADC, along with transistor-level designs of key subcircuits, including operational transconductance amplifiers (OTA), a high-speed comparator, a radiation-tolerant bandgap voltage reference (BGR), a bootstrapped high-linearity sampling switch, and a complete 2.5- bit pipeline stage. This work validated the feasibility of the overall ADC design approach. What is planned for the Phase II project? The Phase II ADC design will lead to a design and fabrication of a chip encompassing an array of 16 ADC channels, each meeting key functionality goals, including 40 MS/s sampling rate, 12-bits resolution at 10.5 11.0 effective number of bits (ENOB), and a very low power dissipation of 12 mW / channel. It will also exceed the required level of TID hardness of 3.5Mrad (Si) as well as achieve extreme tolerance to other radiation effects (e.g., neutron fluencies, SEUs, SEFIs). Commercial Applications and Other Benefits: High performance ADCs hardened to extreme levels of radiation are key components of the LHC experiment, the largest scientific experiment ever constructed. Hundreds of thousands of qualified ADCs will be needed for one detector instrument alone. The currently used ADCs at LHC will be changed to more radiation tolerant and less power consuming ADCs during the upgrade process to High Luminosity Hadron Collider (HL-LHC). Tens of thousands of new radiation hardened, low-power ADCs have been planned to be used in the upgraded Relativistic Heavy Ion Collider (RHIC) as well. Another scientific application for this ADC is NASAs flagship mission to the Jovian moon Europa, as the radiation levels require this type of device. The ADC can be used in defense applications, such as missile control, and federal and commercial space applications. Medical imaging is another application for the ADC


Grant
Agency: Department of Energy | Branch: | Program: SBIR | Phase: Phase II | Award Amount: 1.01M | Year: 2012

A critical aspect in Particle Accelerator Instrumentation is the precise, real-time control of the high- energy particle beams used to create the conditions required for sub-atomic physics experiments. The accelerator instrumentation systems require digital control and feedback with extremely high linearity and dynamic range to achieve system performance targets. In addition, with the added requirements of radiation hardness (because of the devices proximity to the particle beam) and low power (because of the heat generated by densely packed high performance electronics), the analog- to-digital data converter (ADC) is a critical chokepoint that must meet demanding standards. An innovative high performance ADC will be designed and fabricated as a single chip. Based on a novel time-interleaved pipeline architecture developed in Phase I, the ADC will withstand high levels of radiation while providing overall converter performance that exceeds the best conventional (non- rad-hard) ADCs available on the market today. The combinations of performance and radiation tolerance make this ADC ideal to incorporate into particle accelerator instrumentation applications. Phase I saw the design, development, and simulation of a behavioral model of the complete ADC, along with transistor-level designs of key subcircuits. The most important subcircuit, a 3 GS/s track- and-hold amplifier was designed and simulated in the most-advanced silicon germanium fabrication process with accurate transistor models, and its clock jitter, distortion and noise performance clearly exceeds any reported results. A simple test chip was also sent out for fabrication (an achievement beyond the Phase I requirements), and will be verified/tested at the start of Phase II. This program will lead to a programmable, high speed (500 MS/s 3 GS/s), high resolution (12-14 bits) ADC for use in particle accelerator instrumentation applications. The ADC will be highly linear with an INL and DNL of no more than 0.5 LSB, an operating temperature range of at least -10 to 80C, a very high effective number of bits (ENOB) of 11.0, and a total ionization dose (TID) rating of 1 Mrad. These characteristics exceed the requirements of Topic 44g of the DOE SBIR solicitation (12-14 bits, 0.5 2 GS/s) and make this ADC highly suitable for use in particle accelerator instrumentation applications systems, even in the systems where radiation exposure would otherwise degrade performance. Commercial Applications and Other Benefits: This ADC will be well-suited for other DOE nuclear physics and high-energy physics instrumentation. In addition, there is a wide range of both commercial and government applications that demand the combined high performance and radiation tolerance achieved by this design. These include space- based applications such as software-defined radio and satellite systems. The design can be further optimized for conventional, non-rad-hard applications (thus reducing the power and area requirements and boosting even further the circuit performance) to address the most advanced radar and communications systems


Grant
Agency: Department of Defense | Branch: Air Force | Program: SBIR | Phase: Phase II | Award Amount: 1.29M | Year: 2015

ABSTRACT:The ETRS technology developed under the Phase II SBIR program exploits Lean Depot Management System (LDMS) historical data and CCA analysis to enhance the effrciency and effrcacy of the Versatile Depot Automatic Test System (VDATS). Prioritized diagnostic and repair actions achieve cost-avoidance through reduced mean time to repair (MTTR), reduced frequency of no fault found (NFF) codes, increased mean time between maintenance events (MTBE), and increased utilization effrciency of the VDATS platform. The net result is higher asset availability at reduced cost. Examples of relevant beneficiaries include Electronic V/arfare (EV/), communications, and navigation systems where conventional diagnostic methods are not sufficient to ensure cost-effective operational readiness of the aircraft to perform its mission.BENEFIT:The potential cost-avoidance enabled by the Expert Troubleshooting Repair System (ETRS) is conservatively estimated at $2 million per yeff per "bad actor" Circuit Card Assembly (CCA) part number in direct maintenance costs. There are additional savings from reduced indirect logistic and inventory management and increased asset availability. This is based on a very conservative estimate of 100 instances of "bad actor" CCAs, each incurring an average of two unnecessary maintenance actions at a round-trip cost of $10,000 in FY2014 dollars. The costavoidance for just three types of bad actor ALQ-172 CCAs over the next five years is over $30 million (3 CCA x $2Miyear x 5 years). Extending the ETRS technology to other Air Force aircraft and subsystems assets will fuither enhance cost-avoidance.

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