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Belaid I.,University of Nice Sophia Antipolis | Muller F.,University of Nice Sophia Antipolis | Benjemaa M.,Research Unit ReDCAD
Proceedings of the 5th International Workshop on Reconfigurable Communication-Centric Systems on Chip 2010, ReCoSoC 2010 | Year: 2010

The FPGA devices are widely used in reconfigurable computing systems, these devices can achieve high flexibility to adapt themselves to various applications by reconfiguring dynamically portions of the dedicated resources. This adaptation with the application requirements reaches better performance and efficient resource utilization. However, the run-time partial reconfiguration brings more complex partitioning of the FPGA reconfigurable area. This issue implies that efficient task placement algorithm is required. Many on-line and off-line algorithms designed for such partially reconfigurable devices have been proposed to provide efficient hardware task placement. In these previous proposals, the quality of hardware task placement is measured by the resource wastage and task rejection and major of these research works disregard the configuration overhead. Moreover, these algorithms optimize these criteria separately and do not satisfy all goals. These considerations can not reflect the overall situation of placement quality. In this paper, we have interested in off-line placement of hardware tasks in partially reconfigurable devices and we propose a novel three-level resource management for hardware task placement. The proposed off-line resource management is based on mixed integer programming formulation and enhances placement quality which is measured by the rate of task rejection, resource utilization and configuration overhead. Source


Loulou I.,Research Unit ReDCAD | Jmaiel M.,Research Unit ReDCAD | Drira K.,Roche Holding AG | Drira K.,INSA Toulouse | Kacem A.H.,Research Unit ReDCAD
Journal of Systems and Software | Year: 2010

We present P/S-CoM, a formal approach supporting the correct modeling of Publish/Subscribe architectural styles and safe reconfiguration of dynamic architectures for event-based communication. We elaborate a set of patterns and we define the corresponding composition rules to build correct by design Publish/Subscribe styles. The defined patterns and rules respect the principle of information dissemination guaranteeing that the produced information reaches all the subscribed consumers. The patterns are modeled as graphs and the semantics of each pattern and each rule is specified formally in Z notations. We implement these specifications under the Z-Eves theorem prover which we use to prove specification consistency. The Z specification of the designed architectural style is also built by composition by applying the composition rules coded in Z. We consider the interconnection topology between event dispatchers as well as the subscription model using elementary refinements of the style specification. Moreover, we model the reconfiguration of Publish/Subscribe architecture via guarded graph-rewriting rules whose body specifies the structural constraints and whose guards define the pre- and post-conditions ensuring in this way the preservation of stylistic constraints. Similarly, we interpret reconfiguration rules in Z notations, and we implement these rules under Z-Eves for proving that all reconfigurations are style preserving. This results in a unified formal approach which handles both the static and the dynamic aspects of Publish/Subscribe software architectures. © 2009 Elsevier Inc. All rights reserved. Source


Belaid I.,University of Nice Sophia Antipolis | Belaid I.,Research Unit ReDCAD | Muller F.,University of Nice Sophia Antipolis | Muller F.,Research Unit ReDCAD | And 2 more authors.
International Journal of Reconfigurable Computing | Year: 2010

Currently, reconfigurable hardware devices feature a high density of heterogeneous resources to enable multitasking and offer flexibility in application needs. These concepts raise the need for efficient management of hardware tasks and hardware resources. The scheduling of hardware tasks is highly dependent on placement. Placement focuses on allocation of hardware resources required by the scheduled hardware tasks. In this paper, we propose novel three-level resource management that investigates enhancement of placement quality by reducing task rejection, configuration overheads, and by optimizing resource utilization. Improving placement quality will produce significant enhancement of performance for scheduling and overall execution time of the application in FPGA. Hence, the placement problem is formulated into a constrained optimization problem and resolved with powerful solvers using the Branch and Bound method. The obtained results of an application of heterogeneous hardware tasks show an average resource utilization of 36 of the available resources on the reconfigurable region and an overall overhead of 11% of total application running time, and we have eliminated the issue of task rejection. Compared to static implementation, the gain in resource utilization within the reconfigurable region achieves up to 43%. Copyright © 2010 Ikbel Belaid et al. Source

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