Renesas Electronics Corporation

www.renesas.com
Kawasaki, Japan

Renesas Electronics Corporation TYO: 6723 is a Japanese semiconductor manufacturer headquartered in Tokyo. It has manufacturing, design and sales operations in around 20 countries. Renesas is one of the world's largest manufacturers of semiconductor systems for mobile phones and automotive applications. It is the world's largest manufacturer of microcontrollers and the second largest manufacturer of application processors. Renesas is also known for LCD drivers, RF ICs, mixed-signal integrated circuits and system-on-a-chip semiconductors. Wikipedia.

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Patent
Renesas Electronics Corporation | Date: 2016-11-11

A semiconductor apparatus includes an operation oscillator 13, a reference oscillator 16, a first operation switch 11 connected in series with the operation oscillator 13 between a power supply potential VDD and a ground potential GND, a first reference switch 14 connected in series with the reference oscillator 16 between the power supply potential VDD and the ground potential GND, a second reference switch 15 connected in parallel with the reference oscillator 16 between the power supply potential VDD and the ground potential GND, an operation counter 26 configured to count the number of output pulses from the operation oscillator 13 in a measurement period, and a reference counter 25 configured to count the number of output pulses from the reference oscillator 16 in the measurement period.


Patent
Renesas Electronics Corporation | Date: 2017-01-31

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.


Patent
Renesas Electronics Corporation | Date: 2016-12-22

A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (Al) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.


Patent
Renesas Electronics Corporation | Date: 2016-09-13

A semiconductor device with reduced power consumption. The device includes: an n-type well region overlying the main surface of a semiconductor substrate; an element isolation region overlying the main surface; a first and a second active region located in the n-type well region and surrounded by the element isolation region; an insulating film overlying the main surface in the first active region; a semiconductor layer overlying the insulating film; a gate electrode layer overlying the semiconductor layer through a gate insulating film; a p-type source and a drain region formed in the semiconductor layer at both ends of the gate electrode layer; a dummy gate electrode layer overlying the semiconductor layer through the gate insulating film; an n-type semiconductor region overlying an n-type well region surface in the second active region; and a power supply wiring coupled with the n-type semiconductor region. The dummy gate electrode layer is electrically floating.


Patent
Renesas Electronics Corporation | Date: 2017-09-20

A semiconductor device includes: a pad electrode 9a formed in an uppermost layer of a plurality of wiring layers; a base insulating film 11 having an opening 11a on the pad electrode 9a; a base metal film UM formed on the base insulating film 11; a redistribution line RM formed on the base metal film UM; and a cap metal film CM formed so as to cover an upper surface and a side surface of the redistribution line RM. In addition, in a region outside the redistribution line RM, the base metal film UM made of a material different from that of the redistribution line RM and the cap metal film CM made of a material different from the redistribution line RM are formed between the cap metal film CM formed on the side surface of the redistribution line RM and the base insulating film 11, and the base metal film UM and the cap metal film CM are in direct contact with each other in the region outside the redistribution line RM.


Patent
Renesas Electronics Corporation | Date: 2017-09-13

A semiconductor device according to the present invention has a capacitance DAC (Digital-to-Analog Converter) circuit and a comparator. The capacitance DAC circuit includes: first capacitors to which input signals are given and each of which has a capacitance value corresponding to a weight of a bit to be converted; and second capacitors to which common voltages are given and whose sum of capacitance values is equivalent to that of the first capacitors. Further, the second capacitors include: a redundant bit capacitor having a capacitance value corresponding to a weight of a redundant bit; and adjustment capacitors each having a capacitance value obtained by subtracting the capacitance value of the redundant bit capacitor from the sum of the capacitance values of the second capacitors.


Patent
Renesas Electronics Corporation | Date: 2017-09-27

The detection of a fault of the address signal system in memory access is aimed at. A semiconductor device according to the present invention includes an address conversion circuit which generates the second address for storing an error detecting code in a memory based on the first address for storing data; a write circuit which writes data at the first address and writes an error detecting code at the second address; and a read circuit which reads data from the first address, reads the error detecting code from the second address, and detects an error based on the data and the error detecting code. The address conversion circuit generates an address as the second address by modifying the value of at least one bit of the first address so as to offset the storing position of the error detecting code to the storing position of the data, and by inverting the value of or permutating the order of the prescribed number of bits among the other bits.


A semiconductor device capable of preventing deterioration of a transistor caused by a flow of an overcurrent is provided. According to an embodiment, a semiconductor chip includes a first transistor provided between a high-potential side voltage terminal to which a constant voltage generated by reducing a power-supply voltage is supplied and an output terminal, a second transistor provided between a low-potential side voltage terminal to which a ground voltage is supplied and the output terminal, a control circuit controlling turning-on/off of the first and second transistors, a boosting circuit boosting the power-supply voltage by using a voltage of the output terminal to generate an output voltage, and an overvoltage detection circuit detecting an overvoltage of a power-supply line that couples the high-potential side voltage terminal and the first transistor to each other. The control circuit performs control to turn off the second transistor, when the overvoltage has been detected.


Patent
Renesas Electronics Corporation | Date: 2017-09-27

Image processing is made efficient. An image processing apparatus according to an embodiment includes a line memory, a plurality of pipelines, and a line memory control circuit that controls data reading from the line memory to processing units. The processing unit includes a first operator that performs a first arithmetic operation, a second operator which performs a second arithmetic operation based on first intermediate data based on an arithmetic operation result of the first operator and which calculates second intermediate data according to the first intermediate data of when peripheral pixels are sequentially changed, third operators which perform a third arithmetic operation based on the first intermediate data and which calculate third intermediate data according to the first intermediate data of when the peripheral pixels are sequentially changed, and delay elements that delay the third intermediate data.


Patent
Renesas Electronics Corporation | Date: 2017-09-20

A semiconductor device includes: an encoding processing unit that stores an encoded stream of an input data that is encoded based on the specified encoding control information; a buffer management unit that calculates the transmission buffer occupancy indicating the amount of data stored in a transmission buffer according to the generated data amount, and the reception buffer occupancy indicating the amount of data stored in a reception buffer, which is the destination of the encoded stream; and a control information specifying unit that, when the transmission buffer occupancy is equal to or less than a first threshold, specifies the encoding control information based on the reception buffer occupancy, and when the transmission buffer occupancy is greater than the first threshold, specifies the encoding control information to further reduce the generated data amount than in the case of equal to or less than the first threshold, to the encoding processing unit.

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