Kawasaki, Japan

Renesas Electronics Corporation TYO: 6723 is a Japanese semiconductor manufacturer headquartered in Tokyo. It has manufacturing, design and sales operations in around 20 countries. Renesas is one of the world's largest manufacturers of semiconductor systems for mobile phones and automotive applications. It is the world's largest manufacturer of microcontrollers and the second largest manufacturer of application processors. Renesas is also known for LCD drivers, RF ICs, mixed-signal integrated circuits and system-on-a-chip semiconductors. Wikipedia.


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Patent
Renesas Electronics Corporation | Date: 2017-03-01

A property of a semiconductor device having a non-volatile memory is improved. A semiconductor device, which has a control gate electrode part and a memory gate electrode part placed above a semiconductor substrate of a non-volatile memory, is configured as follows. A thick film portion is formed in an end portion of the control gate insulating film on the memory gate electrode part side, below the control gate electrode part. According to this configuration, even when holes are efficiently injected to a comer portion of the memory gate electrode part by an FN tunnel erasing method, electrons can be efficiently injected to the comer portion of the memory gate electrode part by an SSI injection method. Thus, a mismatch of the electron/hole distribution can be moderated, so that the retention property of the memory cell can be improved.


Patent
Renesas Electronics Corporation | Date: 2017-03-01

To provide an LDMOS semiconductor device having improved properties. A semiconductor device having a source region and a drain region, a channel formation region, a drain insulating region between the channel formation region and the drain region, and a gate electrode is provided. The drain insulating region has a slit exposing therefrom an active region and this slit is placed on the side of the channel formation region with respect to the center of the drain insulating region. This active region is formed as an n type semiconductor region. Such a configuration enables relaxation of an electric field of the drain insulating region on the side of the channel formation region (on the side of the source region). The generation number of hot carriers (hot electrons, hot holes) can therefore be reduced. As a result, a semiconductor device having improved HCI-related properties can be obtained.


Patent
Renesas Electronics Corporation | Date: 2017-03-22

A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.


Patent
Renesas Electronics Corporation | Date: 2017-02-15

Performance of a semiconductor device is improved. An element isolation portion includes a projection portion that projects from an SOI substrate and comes into contact with a piled-up layer. The height of the upper surface of the projection portion is configured to be lower than or equal to the height of the upper surface of the piled-up layer and higher than or equal to a half of the height of the upper surface of the piled-up layer with reference to a surface of a silicon layer of the SOI substrate.


Patent
Renesas Electronics Corporation | Date: 2017-03-01

A control system includes an information obtaining apparatus , a network, and a control apparatus. The information obtaining apparatus includes a distance information obtaining unit configured to obtain a distance information indicating a distance to an object and a transmission unit configured to transmit the distance information obtained by the distance information obtaining unit. The control apparatus includes a reception unit configured to receive the distance information transmitted by the transmission unit via the network, a distance information correction unit configured to correct the distance information received by the reception unit, and a control unit configured to perform control using the distance information corrected by the distance information correction unit. The distance information correction unit corrects the distance information based on a time taken from when the distance information is obtained by the distance information obtaining unit until the distance information is input to the distance information correction unit.


Patent
Renesas Electronics Corporation | Date: 2017-02-01

The communication terminal includes a communication interface for acquiring external time information from outside and a non-volatile memory and operates as described below. The communication terminal periodically acquires external time information, encrypts the internal time information calibrated based on the acquired external time information and thereafter writes the encrypted internal time information into the non-volatile memory. In an initialization sequence after power-on of the communication terminal, the communication terminal reads and decrypts internal time information that is lastly written to the non-volatile memory before the power-on, newly acquires external time information and verifies validity of the acquired external time information by comparing the acquired external time information with the read internal time information.


Patent
Renesas Electronics Corporation | Date: 2017-01-11

A semiconductor device includes a data obtaining unit that obtains a plurality of data items each indicating a result of observation from a plurality of radars for observing surroundings, converts the plurality of data items into data items in a polar coordinate format, and stores them in a storage unit, an axial position converting unit that performs conversion on the plurality of data items in the polar coordinate data format stored in the storage unit so that their axial positions will be the same, generates the plurality of data items on which axial position conversion has been performed, and stores them in the storage unit, a data superimposing unit that superimposes the plurality of data items on which the axial position conversion has been performed to generate superimposed data, and a coordinate converting unit that converts the superimposed data into data in a Cartesian coordinate format.


Patent
Renesas Electronics Corporation | Date: 2017-02-22

The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.


Patent
Renesas Electronics Corporation | Date: 2017-03-29

A performance of a semiconductor device is improved. A semiconductor device includes two element portions and an interposition portion interposed between the two element portions. The interposition portion includes a p-type body region formed in a part of a semiconductor layer, the part being located between two trenches, and two p-type floating regions formed in two respective parts of the semiconductor layer, the two respective portions being located on both sides of the p-type body region via the two respective trenches. A lower end of the p-type floating region is arranged on a lower side with reference to a lower end of the p-type body region.


Patent
Renesas Electronics Corporation | Date: 2017-04-05

Properties of a semiconductor device are improved. A semiconductor device is configured so as to have a protective film (PRO1) provided over an interconnection (M1) and having an opening (OA1), and a plating film (OPM1) provided in the opening (OA1). A slit (SL) is provided in a side face of the opening (OA1), and the plating film (OPM1) is also disposed in the slit (SL). Thus, the slit is provided in the side face of the opening (OA1), and the plating film (OPM1) is also grown in the slit (SL). This results in a long penetration path of a plating solution during subsequent formation of the plating film (OPM1). Hence, a corroded portion is less likely to be formed in the interconnection (pad region). Even if the corroded portion is formed, a portion of the slit (SL) is corroded prior to the interconnection (pad region) at a sacrifice, making it possible to suppress expansion of the corroded portion into the interconnection (M1) pad region).

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