Kawasaki, Japan

Renesas Electronics Corporation TYO: 6723 is a Japanese semiconductor manufacturer headquartered in Tokyo. It has manufacturing, design and sales operations in around 20 countries. Renesas is one of the world's largest manufacturers of semiconductor systems for mobile phones and automotive applications. It is the world's largest manufacturer of microcontrollers and the second largest manufacturer of application processors. Renesas is also known for LCD drivers, RF ICs, mixed-signal integrated circuits and system-on-a-chip semiconductors. Wikipedia.


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Patent
Renesas Electronics Corporation | Date: 2017-01-25

The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.


Patent
Renesas Electronics Corporation | Date: 2017-01-12

An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.


Patent
Renesas Electronics Corporation | Date: 2017-01-13

A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.


Patent
Renesas Electronics Corporation | Date: 2017-01-11

Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.


Patent
Renesas Electronics Corporation | Date: 2017-01-11

Power supply of ECUs connected to a communication network is optimally controlled so that power consumption is reduced. A transceiver/receiver converts a message of a differential signal received via a CAN bus into a digital signal. A select circuit determines whether the converted message is in a CAN format or a UART format. If it is in the UART format, the select circuit outputs a message to the UART circuit. A UART circuit determines whether the message matches a UART format. If matched, an ID determination circuit determines whether the input message is specifying a CAN ID of its own ECU. If it is the CAN ID of the ECU, the ID determination circuit outputs an enable signal to turn on a regulator and supply power to an MCU and an actuator.


Patent
Renesas Electronics Corporation | Date: 2017-01-31

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.


Patent
Renesas Electronics Corporation | Date: 2017-02-03

A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy wires formed in an uppermost layer of the first plurality of the wiring layers, and a second semiconductor chip including a second plurality of wiring layers, a second coil, a second bonding pad, and second dummy wires formed in an uppermost layer of the second plurality of the wiring layers. The first semiconductor chip and the second semiconductor chip face each other via an insulation sheet. The first coil and the second coil are magnetically coupled with each other.


Patent
Renesas Electronics Corporation | Date: 2017-02-08

In a semiconductor device, received signals of different frequency bands are input selectively to low noise amplifiers. A plurality of primary inductors are coupled between differential output nodes of the respective low noise amplifiers. A secondary inductor is provided commonly for the primary inductors, and magnetically coupled to the primary inductors. A demodulator converts a received signal transmitted from one of the primary inductors to the secondary inductor by electromagnetic induction, into a signal of a low frequency.


A semiconductor device includes a memory for storing a plurality of instructions therein, an instruction queue which temporarily stores the instructions fetched from the memory therein, a central processing unit which executes the instruction supplied from the instruction queue, an instruction cache which stores therein the instructions executed in the past by the central processing unit, and a control circuit which controls fetching of each instruction. When the central processing unit executes a branch instruction, and an instruction of a branch destination is being in the instruction cache and an instruction following the instruction of the branch destination is stored in the instruction queue, the control circuit causes the instruction queue to fetch the instruction of the branch destination from the instruction cache and causes the instruction queue not to fetch the instruction following the instruction of the branch destination.


Patent
Renesas Electronics Corporation | Date: 2017-02-03

Technology to suppress the drop in SIMD processor efficiency that occurs when exchanging two-dimensional data in a plurality of rectangular regions, between an external section and a plurality of processor elements in an SIMD processor, so that one rectangular region corresponds to one processor element. In the SIMD processor, an address storage unit in a memory controller is capable of setting N number of addresses Ai (i=1 through N) in an external memory by utilizing a control processor. A parameter storage unit is capable of setting a first parameter OSV, a second parameter W, and a third parameter L by utilizing a control processor. A data transfer unit executes the transfer of data between an external memory, and the buffers in N number of processor elements contained in the applicable SIMD processor, based on the contents of the address storage unit and the parameter storage unit.

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