Recore Systems BV

Enschede, Netherlands

Recore Systems BV

Enschede, Netherlands

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Grant
Agency: European Commission | Branch: FP7 | Program: NOE | Phase: ICT-2011.3.4 | Award Amount: 3.81M | Year: 2012

The proposed HiPEAC network of excellence is a follow-up of an existing network and wants (i) to steer and to increase the European research in computing systems; (ii) to improve the quality of the European computing systems research, and (iii) to create a visible and integrated pan-European community in computing systems. The network is structured along four programs. The membership program aims at growing the network. It will focus on the creation of a vibrant industrial membership, and it will reach out to the companies and academics in the new member states. It wants to increasingly organize events in new member states. The mobility program aims at bringing the partners and the members closer together. The mobility program supports two types of mobility: (i) exchanges of one to three months like internships, collaboration grants, mini-sabbaticals, and (ii) public networking events like computing systems weeks, sometimes collocated with other events (project meetings, conference, ...). The research coordination program aims at coordinating the joint research between the HiPEAC members. A tangible result of the research coordination is the bi-annual HiPEAC vision. It also wants to support the European low-power industry by promoting their platform ecosystem and it wants to proactively prepare the HiPEAC community for the impact of technological evolutions on computing systems (like photonics, new memory types, ...). It also runs a set of thematic workgroups on the different technical challenges and solutions from the HiPEAC roadmap. The visibility program manages all the public activities of the network such as the conference, the summer school, the website, the newsletter, the award program, the dissemination of research results, ... It wants (i) to proactively approach the specialized press, (ii) to grow the conference into a much bigger event, (iii) to make the HiPEAC institutions more attractive for top talent by creating a job portal.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2011.9.8 | Award Amount: 2.88M | Year: 2012

SENSATION aims at increasing the scale of systems that are self-supporting by balancing energy harvesting and consumption up to the level of complete products. In order to build such Energy Centric Systems, embedded system designers face the quest for optimal performance within acceptable reliability and tight energy bounds. Programming systems that reconfigure themselves in view of changing tasks, resources, errors and available energy is a demanding challenge.\nThe lack of effective design-time support for taking on this challenge obstructs the creativity and productivity of design teams. This is an impediment to European companies developing embedded components, devices, and platforms, and is a major obstacle to developing self-supporting systems.\n\nSENSATION will free the system design process by devising energy-centric modeling and optimization tools for the design of resource-optimal reliable systems. This depends on orchestrated, non-incremental progress in several research domains. The project combines Europes leading scientists in model-based quantitative evaluation and optimization, and in low-power reconfigurable systems.\n\nSENSATION provides automated analysis and synthesis tools for energy-centric systems. For the first time, tools for optimizing performance and reliability will be integrated with energy analysis. Based on efficient model-checking algorithms and massive design space exploration, this leads to a many-fold increase in system design productivity.\n\nTwo industrial partners, GomSpace and Recore Systems provide challenging case studies and serve as\nindustrial testbeds. The yardstick for the impact of SENSATION is a reduction in energy consumption by 50%\nand a reduction in time-to-market of at least 10%. An European institutes specializing in embedded systems,\nCISS, actively contributes to the development of the technology and its effective dissemination and industrial\nadoption.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-04-2015 | Award Amount: 3.89M | Year: 2016

Increasing performance and reducing costs, while maintaining safety levels and programmability are the key de-mands for embedded and cyber-physical systems in European domains, e.g. aerospace, automation, and automotive. For many applications, the necessary performance with low energy consumption can only be provided by customized computing platforms based on heterogeneous many-core architectures. However, their parallel programming with time-critical embedded applications suffers from a complex toolchain and programming process. ARGO (WCET-Aware PaRallelization of Model-Based Applications for HeteroGeneOus Parallel Systems) will ad-dress this challenge with a holistic approach for programming heterogeneous multi- and many-core architectures using automatic parallelization of model-based real-time applications. ARGO will enhance WCET-aware automatic parallelization by a cross-layer programming approach combining automatic tool-based and user-guided parallelization to reduce the need for expertise in programming parallel heterogeneous architectures. The ARGO approach will be assessed and demonstrated by prototyping comprehensive time-critical applications from both aerospace and industrial automation domains on customized heterogeneous many-core platforms. The challenging research and innovation action will be achieved by the unique ARGO consortium that brings together industry, leading research institutes and universities. High class SMEs such as Recore Systems, Scilab Enterprises and AbsInt will contribute their diverse know-how in heterogeneous many-core technologies, model-based design environments and WCET calculation. The academic partners will contribute their outstanding expertise in code transformations, automatic parallelization and system-level WCET analysis.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2007.3.4 | Award Amount: 4.40M | Year: 2008

The CRISP (Cutting edge Reconfigurable ICs for Stream Processing) project researches optimal utilization, efficient programming and dependability of reconfigurable many-cores for streaming applications. The project has four central themes: Streaming Applications, General Stream Processor (GSP), Run-time Mapping and Dependability.\n1) Streaming applications range from low-end consumer electronics and automotive applications to demanding high-end medical and defence applications. In CRISP, beamforming and satellite navigation are used for proof of concept.\n2) Tomorrows GSP is to be prototyped in CRISP. The GSP is a dynamically reconfigurable many-core for streaming applications. It offers flexibility, high performance, low power, a small footprint and design tools support.\n3) Computational resource utilization in a many-core can be dramatically improved by dynamic hardware/software partitioning at run-time. This also enables: upgrading, bug fixing and hardware fault diagnosis and repair.\n4) Dependability and yield of deep-submicron chips are improved using new techniques for static and dynamic detection and localization of faults and (dynamically) circumventing faulty hardware.\nThe partners (Recore, Uni. Twente, Atmel, Thales, Tampere Uni. and NXP) in the small and decisive CRISP consortium complement each other and collaborated successfully in the past. Due to a clear common vision, a full description of work is already agreed.\nDissemination and exploitation are principal in the CRISP project. Europe can benefit quickly from CRISP, as the major project innovations will be applied directly in commercially available reconfigurable technology.\nStreaming applications have very high market potentials and will drive demand for reconfigurable platform chips. CRISP contributes to European excellence in streaming applications and presumably increases European market shares of inexpensive stream processing platforms and allows Europe to achieve a world leading position.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2011.3.4 | Award Amount: 4.43M | Year: 2011

The mapping process of high performance embedded applications to todays multiprocessor system on chip devices suffers from a complex toolchain and programming process. The problem here is the expression of parallelism with a pure imperative programming language which is commonly C. This traditional approach limits the mapping, partitioning and the generation of optimized parallel code, and consequently the achievable performance and power consumption of applications from different domains. The Architecture oriented paraLlelization for high performance embedded Multicore systems using scilAb (ALMA) project aims to bridge these hurdles through the introduction and exploitation of a Scilab-based toolchain which enables the efficient mapping of applications on multiprocessor platforms from high level of abstraction. This holistic solution of the toolchain allows the complexity of both the application and the architecture to be hidden, which leads to a better acceptance, reduced development cost and shorter time-to-market. Driven by the technology restrictions in chip design, the end of Moores law and an unavoidable increasing request of computing performance, ALMA is a fundamental step forward in the necessary introduction of novel computing paradigms and methodologies. ALMA helps to strengthen the position of the EU in the world market of multiprocessor targeted software toolchains. The challenging research will be achieved by the unique ALMA consortium which brings together industry and academia. High class partners from industry such as Recore and Intracom, will contribute their expertise in reconfigurable hardware technology for multi-core systems-on-chip, software development tools and real world applications. The academic partners will contribute their outstanding expertise in reconfigurable computing and compilation tools development.


Grant
Agency: European Commission | Branch: H2020 | Program: RIA | Phase: ICT-01-2014 | Award Amount: 4.00M | Year: 2015

In IMMORTAL, a consortium of leading European academic and industrial players aim at combining their expertise in developing an integrated, cross-layer modelling based tool framework for fault management, verification and reliable design of dependable Cyber-Physical Systems (CPS). Recently, the world has seen emerging CPS modelling frameworks addressing various design aspects such as control, security, verification and validation. However, there have been no considerations for reliability and automated debug aspects of verification. The main aim is to fill this gap by introducing reliable design and automated system debug into CPS modelling. To reach this aim, the project will develop a cross-layer CPS model spanning device (analogue and digital), circuit, network architecture, firmware and software layers. In addition, a holistic fault model for fundamentally different error sources in CPSs (design bugs, wear-out and environmental effects) in a uniform manner will be proposed. Moreover, IMMORTAL plans to develop fault management infrastructure on top of the reliable design framework that would allow ultra-fast fault detection, isolation and recovery in the emerging many-core based CPS networked architectures that are expected to be increasingly adopted in the coming years. As a result, the project will enable development of dependable CPSs with improved reliability and extended effective life-time, ageing and process variations. In line with the expected impacts of the Call, the project will have a significant impact in development time as well as maintenance costs of dependable cyber-physical systems. The tool framework to be developed will be evaluated on a clearly specified real-world use-case of a satellite on-board-computer. However, since the results are more general and applicable to many application domains, including avionics, automotive and telecommunication, demonstration of the framework tools will be applied to CPS examples from other domains as well.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2013.3.4 | Award Amount: 4.17M | Year: 2013

POLCA explicitly addresses the programmability concerns of both embedded and high performance computing. Both domains have generated strongly focused approaches for solving their specific problems that are now confronted with the increasing need for parallelism even in Embedded Systems and the need for addressing non-functional criteria in High Performance Computing. Rather than improving both domains separately, POLCA takes a bold step forward by proposing a hybrid programming model that decisively increases programming efficiency in both areas and enables realisation of multi domain use cases.\nThis model thereby allows efficient parallelisation and distribution of the application code across a highly heterogeneous infrastructure, not through automagic methods, but through exploitation of fundamental mathematical axioms behind the execution logic. The model is strongly oriented towards mathematical application cases of both domains, ranging from sensor evaluation, over monitoring-control-loops to complex simulation and modelling. POLCA is thereby explicitly geared towards exploitation of reconfigurable hardware to make use of their high efficiency under the right usage criteria. In principal it even allows for exploitation of run-time reconfigurations, given an application with a suitable profile.\nThus, POLCA is strongly coupled with a performance evaluation toolchain that supports the right compilation and deployment, and thus execution configuration. To maintain controllability and ensure proper, reliable execution of the non-functional criteria, POLCA can generate stand-alone code that does not require support through virtualisation technologies, but addresses the specifics of the destination platform directly.\nThe project builds up on existing collaboration between experts from embedded computing and high performance computing, to combine complementary expertise from the two domains into an accessible and productive programming model of the future.


She D.,TU Eindhoven | He Y.,TU Eindhoven | He Y.,Recore Systems B.V. | Waeijen L.,TU Eindhoven | Corporaal H.,TU Eindhoven
Journal of Signal Processing Systems | Year: 2015

Energy efficiency is one of the most important metrics in embedded processor design. The use of wide SIMD architecture is a promising approach to build energy-efficient high performance embedded processors. In this paper, we propose a design framework for a configurable wide SIMD architecture that utilizes an explicit datapath to achieve high energy efficiency. The framework is able to generate processor instances based on architecture specification files. It includes a compiler to efficiently program the proposed architecture with standard programming languages including OpenCL. This compiler can analyze the static memory access patterns in OpenCL kernels, generate efficient mappings, and schedule the code to fully utilize the explicit datapath. Extensive experimental results show that the proposed architecture is efficient and scalable in terms of area, performance, and energy. In a 128-PE SIMD processor, the proposed architecture is able to achieve up to 200 times speed-up and reduce the total energy consumption by 50 % compared to a basic RISC processor. © 2014, Springer Science+Business Media New York.


Waeijen L.,TU Eindhoven | She D.,TU Eindhoven | Corporaal H.,TU Eindhoven | He Y.,TU Eindhoven | He Y.,Recore Systems B.V.
Proceedings - Design Automation Conference | Year: 2014

It has been shown that wide Single Instruction Multiple Data architectures (wide-SIMDs) can achieve high energy efficiency, especially in domains such as image and vision processing. In these and various other application domains, reduction is a frequently encountered operation, where mul-tiple input elements need to be combined into a single ele-ment by an associative operation, e.g. addition or multipli-cation. There are many applications that require reduction such as: partial histogram merging, matrix multiplication and min/max-finding. Wide-SIMDs contain a large number of processing elements (PEs), which in general are connected by a minimal form of interconnect for scalability reasons. To efficiently support reduction operations on wide-SIMDs with such a minimal interconnect, we introduce two novel reduction algorithms which do not rely on complex commu-nication networks or any dedicated hardware. The proposed approaches are compared with both dedicated hardware and other software solutions in terms of performance, area, and energy consumption. A practical case study demonstrates that the proposed software approach has much better gener-ality, exibility and no additional hardware cost. Compared to a dedicated hardware adder tree, the proposed software approach saves 6.8% area with a performance penalty of only 6.5%. Copyright 2014 ACM.


Grant
Agency: European Commission | Branch: FP7 | Program: CP | Phase: ICT-2011.3.4 | Award Amount: 3.57M | Year: 2011

DeSyRe will perform research on the design of future reliable Systems-on-Chip (SoCs). These are systems that guarantee continuous and correct operation in the existence of different types of faults. It is a well known fact that various systems are extremely sensitive to faults. Typical examples are medical (i.e. implantable cardiac pacemakers) or automotive systems (i.e. vehicle stability control), in which the shortest stop in operation will cause dramatic damages. Therefore, such applications require a fault-tolerant system, which guarantees correct and reliable functioning at any time.However, as semiconductor technology scales, chips are becoming ever less reliable; prominent reasons for this phenomenon are the sheer number of transistors on a given silicon area and their shrinking device features. As a consequence, fault tolerance, e.g. provided through various redundancy schemes, has an enormously increasing power and performance cost. To make matters worse, power-density is becoming a significant limiting factor for performance and SoC design in general. In the face of such changes in the technological landscape, current solutions for fault-tolerance are expected to introduce an excessive overhead in future SoCs. Attempting to design and manufacture a totally fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the performance and power consumption of a system.DeSyRe will build new, more efficient, adaptive fault-tolerant SoCs delivering a new generation of by design, on-demand reliable systems. Compared to existing approaches, the DeSyRe objective is to reduce the power and performance overheads of fault-tolerance by 10-20%, as well as to improve yield by decreasing the number of defective chips by 10-40%.The above will be achieved through the design of fault-tolerant systems built out of unreliable components, rather than aiming at totally fault-free chips. DeSyRe systems will be on-demand adaptive to various types and densities of faults, as well as to other system constraints and application requirements. For leveraging on-demand adaptation/customization and reliability at reduced cost, a new dynamically reconfigurable substrate will be designed and combined with runtime system software support. The developed design will be demonstrated for two medical SoCs with high reliability constraints and diverse performance and power requirements.The SMEs of the project will exploit the various results of the project in their respective domains. It is expected that they will strengthen their market position and competitiveness having a multiple return on investment. The universities and research organizations will stay on the forefront of research in using the results. The project will strongly contribute in substantiating their prestige in the scientific community. The European citizens will benefit from cheaper hardware and lower power consumption of various consumer goods.

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